【NVIDIA社招】数字后端工程师岗位-北京

NVHR

Hi All,

NVIDIA目前招聘ASIC Physical Design Engineer （后端工程师）啦！！ 北京上海均有空缺！！

北京： 2年以上工作经验    -北京市建国门外大街1号国贸大厦

上海： 2年以上工作经验    -浦东新区秋月路26号

职位描述如下，有意者欢迎发送简历到 tracyw@nvidia.com       QQ: 1751315121


公司介绍
http://www.nvidia.cn/object/about-nvidia-cn.html
在二十年的时间里，NVIDIA 一直在视觉计算方面 (计算机图形的艺术与科学) 勇当先锋。
凭借我们发明的 GPU ——现代视觉计算的引擎，这一领域现已扩张到涵盖了视频游戏、电影制作、产品设计、医学诊断以及科学研究等等。
现在，视觉计算正变得越来越重要，它影响着人们与科技之间的互动方式。

Senior/Physical Design Engineer--Description
As senior role in physical design for NVIDIA GPU and Mobile chips.
Participate in various aspects of physical design, including full chip floor planning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification.
Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention
Collaborate with RTL, DFT and Circuit designers to ensure the high quality of design implementation and optimization.

Minimum requirements:
BS in Engineering or Science.
Power user of EDA tools from Synopsys (ICC/DC/PT/STAR-RC), Cadence (EDI/EPS) or Mentor (Olympus-SOC).
Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and Verification on 40nm, or 28nm technology.
Years of experience in above areas.

Prefer Requirements:
MS in Engineering or Science.
Knowledge in 20nm or FinFET technology, circuit design, and package design.
Experience in physical verification tools from Synopsys (ICV/Mojave) or Mentor (Calibre).
Proficiency in Perl, TCL and Makefile scripts.