DFT 工程师

jj_seu

DFT 工程师@上海
苏州
北京

简历发
芯得
爱德华  [url=mailtoffer@hi-talent.net]offer@hi-talent.net[/url]  

Responsibilities:

1. Participate in SoC level DFTarchitecture definition.

2. Implement DFT strategy for the SoCchips, cooperating with design team

3. Implement basic DFT schemes, includingscan, IP test, JTAG, Mem BIST and Logic BIST.

4. Develop the high coverage and costeffective test patterns.

5. Verify all DFT logics and test patternswith simulation and static timing analysis tool.

6. Support other teams for DFT relatedproblems.

Position Requirements:

1. BS (MS preferred) in microelectronics,electrical engineering or equivalent with 4+ years of DFT design experience,preferably with large SoC chips.

2. Handy experience on scan, mbist, lbist,JTAG, boundary scan, ATPG, DFT for IPs and RTL/gate simulation. 3. Experienceon Power processor is a strong plus.

4. STA and RTL design experience is astrong plus. 5. ATE tester experience is a plus. 6. Must be able to communicatein both written and spoken English.

7. Good team work spirit and communicationskill.

Best Regards

Jane.Jin金娟

Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.

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skjeon78

thanks a lot