【NVIDIA社招】前端逻辑设计工程师(ASIC)

NVHR

Hello All,

这边是NVIDIAHR Tracy,
我们目前在上海招聘前端逻辑工程师
,
职位描述如下，欢迎有意向者投递，社招岗位，2年以上工作经验；

简历投递：
tracyw@nvidia.com

QQ:  1751315121

XBAR ASIC Design Engineer-Shanghai

Description/Qualifications:

Job Description/Qualifications:

The ASIC design engineer is expected to co-work witharchitect to define architecture/micro-architecture, do RTL implementation andfunctional verification

Required Skills: Ability to communicate technicalsubjects in both written and oral form

Strong Verilog and Perl programing skills.

Good Understanding of RTL synthesis and simulation toolsand gate level debug.

Good Understanding of low power design technology.

Experience with Simulation Tools – Cadence NCSIM,Synopsys VCS or similar.

Experience with Synthesis Tools – Synopsys DesignCompiler /DCT/DC Ultra or similar Excellent written and spoken English Language.

Self-motivated and work patiently.

Desirable Skills:

Some appreciation of Makefile, Shelland C++ programing skills.

Good knowledge and experience withmulti-clock design.

Good knowledge and experience ofinterface handshake protocol.

Knowledge of bus design.

Knowledge of arbitration design.

Experience of scripting workingenvironment.

BestRegards

Tracy

QQ:1751315121

Mail:tracyw@nvidia.com

NVHR

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