招聘验证工程师

Cissy_pq

[size=18.6666660308838px]感兴趣可发简历至 cissy_pq@163.com

SeniorVerification Engineer

Common:

1)    Familiarwith system Verilog and UVM methodology

2)    Familiarwith UNIX/Linux shell

3)    Familiarwith Perl script

4)    Providetest plan basing on the design spec

5)    Setupthe module level and chip level DV environment

6)    RTLsimulation and netlist with timing simulation

7)    Implementthe test cases basing test plan, and provide the test coverage

8)    Workwith design team to repeat the failure case and find out root cause

Position 1:

1)    Familiarwith the PCIe and NVMe protocol

2)    Familiarwith SATA protocol

3)    Familiarwith the NAND behavior and ONFI protocol

4)    Knowledgeon ARM9 CPU core and AHB bus

5)    Knowledgeon DDR3/LPDDR2

6)    Knowledgeon AES and BCH ECC will be a plus

Position 2:

1)    Familiarwith eMMC protocol

2)    Familiarwith the NAND behavior and ONFI protocol

3)    Knowledgeon BCH ECC

Postion 3:

1)    Familar with mixed signal design and/orverification

Postion 4:

1) Familar with one of the areas below:

a. ARM A9 subsystem

b. DDR3/DDR4

c. USB 3.0

d. SATA

e. PCIe

f. Ethernet

（work inShanghai or Beijing）

xzw_e

实习生要吗

Cissy_pq

回复 2# xzw_e


    我们需要有经验的工程师，谢谢！