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本帖最后由 ariabell 于 2015-7-17 09:14 编辑
Job Title：Synopsys DDR PHY digital verification engineer
Location：Wuhan
Email:jobs-china@synopsys.com
Job description Develop and execute verification for IP level functional features related to Interface IP system. Work closely with Design/Macro teams to identify the milestones and quality metrics of the project that includes scoping, tracking and delivery. Participate in test environment infra and regression infra development, test bench development in VMM/UVM/System Verilog/C++,test cases development and debug. Provide technical direction to team members with respect to verification methodologies,verification environment capabilities, test planning, result analysis to enable the most effective verification flow. The candidate will work in a project and team oriented environment with teams spread across multiple sites, worldwide.
Requirements Must have BSEE in EE with 5+ years of relevant experience or MSEE with 3+ years of relevant experience in the following areas:
Verification experience of ASIC interface design or mix-signal system. Hands on experience with System Verilog/ VERA coding and Simulation tools;knowledge of C++/ OOPs concepts. Has good analysis and problem-solving skills Knowledge of Perl/Shell/Makefile scripts. Knowledge of design for verification and design for Lowpower. Team player with good communication skills of both verbal and written English. Previous team or technical leadership experience on verification is a plus.
欢迎将简历投递到 jobs-china@synopsys.com. 关注我们的微信公众号：新思科技招聘。内有大量ERP内推职位，欢迎关注！ | 
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发表于 2015-7-15 17:25:28
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