Embedded hardware know it all

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Elsevier出版社08年的know it all系列中的一本
Embedded Hardware (Newnes Know It All).pdf (10.3 MB, 下载次数: 112 )

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目录如下：
About the Authors ....................................................................................................................xiii
Chapter 1: Embedded Hardware Basics ..................................................................................... 1
1.1 Lesson One on Hardware: Reading Schematics ............................................................ 1
1.2 The Embedded Board and the von Neumann Model .................................................... 5
1.3 Powering the Hardware ................................................................................................. 9
1.3.1 A Quick Comment on Analog Vs. Digital Signals ............................................ 10
1.4 Basic Electronics ......................................................................................................... 12
1.4.1 DC Circuits ........................................................................................................ 12
1.4.2 AC Circuits ........................................................................................................ 21
1.4.3 Active Devices ................................................................................................... 28
1.5 Putting It Together: A Power Supply .......................................................................... 32
1.5.1 The Scope .......................................................................................................... 35
1.5.2 Controls .............................................................................................................. 35
1.5.3 Probes ................................................................................................................. 38
Endnotes ............................................................................................................................. 41
Chapter 2: Logic Circuits .......................................................................................................... 43
2.1 Coding ......................................................................................................................... 43
2.1.1 BCD .................................................................................................................. 46
2.2 Combinatorial Logic .................................................................................................... 47
2.2.1 NOT Gate .......................................................................................................... 47
2.2.2 AND and NAND Gates ..................................................................................... 48
2.2.3 OR and NOR Gates ........................................................................................... 49
2.2.4 XOR .................................................................................................................. 50
2.2.5 Circuits .............................................................................................................. 50
2.2.6 Tristate Devices ................................................................................................. 53
2.3 Sequential Logic .......................................................................................................... 53
2.3.1 Logic Wrap-Up ................................................................................................. 57
2.4 Putting It All Together: The Integrated Circuit ........................................................... 58
Endnotes ............................................................................................................................. 61
Chapter 3: Embedded Processors .............................................................................................. 63
3.1 Introduction ................................................................................................................. 63
3.2 ISA Architecture Models ............................................................................................. 65
3.2.1 Operations ......................................................................................................... 65
3.2.2 Operands ........................................................................................................... 68
3.2.3 Storage .............................................................................................................. 69
3.2.4 Addressing Modes ............................................................................................. 71
3.2.5 Interrupts and Exception Handling ................................................................... 72
3.2.6 Application-Specifi c ISA Models ..................................................................... 72
3.2.7 General-Purpose ISA Models ........................................................................... 74
3.2.8 Instruction-Level Parallelism ISA Models ........................................................ 76
3.3 Internal Processor Design ............................................................................................ 78
3.3.1 Central Processing Unit (CPU) ......................................................................... 82
3.3.2 On-Chip Memory .............................................................................................. 99
3.3.3 Processor Input/Output (I/O)........................................................................... 113
3.3.4 Processor Buses ............................................................................................... 130
3.4 Processor Performance .............................................................................................. 131
3.4.1 Benchmarks ..................................................................................................... 133
Endnotes ........................................................................................................................... 133
Chapter 4: Embedded Board Buses and I/O ........................................................................... 137
4.1 Board I/O ................................................................................................................... 137
4.2 Managing Data: Serial vs. Parallel I/O ...................................................................... 140
4.2.1 Serial I/O Example 1: Networking and Communications: RS-232 ................ 144
4.2.2 Example: Motorola/Freescale MPC823 FADS Board
RS-232 System Model .................................................................................... 146
4.2.3 Serial I/O Example 2: Networking and Communications:
IEEE 802.11 Wireless LAN ............................................................................ 148
4.2.4 Parallel I/O ...................................................................................................... 153
4.2.5 Parallel I/O Example 3: “Parallel” Output and Graphics I/O ......................... 153
4.2.6 Parallel and Serial I/O Example 4: Networking and
Communications—Ethernet ............................................................................ 156
4.2.7 Example 1: Motorola/Freescale MPC823 FADS Board
Ethernet System Model ................................................................................... 158
4.2.8 Example 2: Net Silicon ARM7 (6127001) Development
Board Ethernet System Model ........................................................................ 160
4.2.9 Example 3: Adastra Neptune x86 Board Ethernet System Model .................. 161
4.3 Interfacing the I/O Components ................................................................................ 161
4.3.1 Interfacing the I/O Device with the Embedded Board .................................... 162
4.3.2 Interfacing an I/O Controller and the Master CPU ......................................... 164
4.4 I/O and Performance ................................................................................................. 165
4.5 Board Buses ............................................................................................................... 166
4.6 Bus Arbitration and Timing ....................................................................................... 168
4.6.1 Nonexpandable Bus: I2C Bus Example .......................................................... 174
4.6.2 PCI (Peripheral Component Interconnect)
Bus Example: Expandable ..............................................................................175
4.7 Integrating the Bus with Other Board Components .................................................. 179
4.8 Bus Performance ....................................................................................................... 180
Chapter 5: Memory Systems ................................................................................................... 183
5.1 Introduction ............................................................................................................... 183
5.2 Memory Spaces ......................................................................................................... 183
5.2.1 L1 Instruction Memory ................................................................................... 186
5.2.2 Using L1 Instruction Memory for Data Placement ......................................... 186
5.2.3 L1 Data Memory ............................................................................................. 187
5.3 Cache Overview ........................................................................................................ 187
5.3.1 What Is Cache? ............................................................................................... 188
5.3.2 Direct-Mapped Cache ..................................................................................... 190
5.3.3 Fully Associative Cache .................................................................................. 190
5.3.4 N-Way Set-Associative Cache ........................................................................ 191
5.3.5 More Cache Details ......................................................................................... 191
5.3.6 Write-Through and Write-Back Data Cache................................................... 193
5.4 External Memory ....................................................................................................... 195
5.4.1 Synchronous Memory ..................................................................................... 195
5.4.2 Asynchronous Memory ................................................................................... 203
5.4.3 Nonvolatile Memories ..................................................................................... 206
5.5 Direct Memory Access .............................................................................................. 214
5.5.1 DMA Controller Overview ............................................................................. 215
5.5.2 More on the DMA Controller ......................................................................... 216
5.5.3 Programming the DMA Controller ................................................................. 218
5.5.4 DMA Classifi cations ....................................................................................... 228
5.5.5 Register-Based DMA ...................................................................................... 228
5.5.6 Descriptor-Based DMA .................................................................................. 231
5.5.7 Advanced DMA Features ................................................................................ 234
Endnotes ........................................................................................................................... 236
Chapter 6: Timing Analysis in Embedded Systems ................................................................ 239
6.1 Introduction ............................................................................................................... 239
6.2 Timing Diagram Notation Conventions .................................................................... 239
6.2.1 Rise and Fall Times ......................................................................................... 241
6.2.2 Propagation Delays ......................................................................................... 241
6.2.3 Setup and Hold Time....................................................................................... 241
6.2.4 Tri-State Bus Interfacing ................................................................................. 243
6.2.5 Pulse Width and Clock Frequency .................................................................. 244
6.3 Fan-Out and Loading Analysis: DC and AC ............................................................. 244
6.3.1 Calculating Wiring Capacitance ...................................................................... 247
6.3.2 Fan-Out When CMOS Drives LSTTL ............................................................ 249
6.3.3 Transmission-Line Effects .............................................................................. 251
6.3.4 Ground Bounce ............................................................................................... 253
6.4 Logic Family IC Characteristics and Interfacing ...................................................... 255
6.4.1 Interfacing TTL Compatible Signals to 5 V CMOS ....................................... 258
6.5 Design Example: Noise Margin Analysis Spreadsheet ............................................. 261
6.6 Worst-Case Timing Analysis Example ...................................................................... 270
Endnotes ........................................................................................................................... 272
Chapter 7: Choosing a Microcontroller and Other Design Decisions .................................... 273
7.1 Introduction ............................................................................................................... 273
7.2 Choosing the Right Core ........................................................................................... 276
7.3 Building Custom Peripherals with FPGAs ................................................................ 281
7.4 Whose Development Hardware to Use—Chicken or Egg? ....................................... 282
7.5 Recommended Laboratory Equipment ...................................................................... 285
7.6 Development Toolchains ........................................................................................... 286
7.7 Free Embedded Operating Systems .......................................................................... 289
7.8 GNU and You: How Using “Free” Software Affects Your Product .......................... 295
Chapter 8: The Essence of Microcontroller Networking: RS-232 .......................................... 301
8.1 Introduction ............................................................................................................... 301
8.2 Some History ............................................................................................................. 303
8.3 RS-232 Standard Operating Procedure ..................................................................... 305
8.4 RS-232 Voltage Conversion Considerations ............................................................. 308
8.5 Implementing RS-232 with a Microcontroller .......................................................... 310
8.5.1 Basic RS-232 Hardware .................................................................................. 310
8.5.2 Building a Simple Microcontroller RS-232 Transceiver ................................ 313
8.6 Writing RS-232 Microcontroller Routines in BASIC ............................................... 333
8.7 Building Some RS-232 Communications Hardware ................................................. 339
8.7.1 A Few More BASIC RS-232 Instructions ....................................................... 339
8.8 I2C: The Other Serial Protocol .................................................................................. 342
8.8.1 Why Use I2C? .................................................................................................. 343
8.8.2 The I2C Bus ..................................................................................................... 344
8.8.3 I2C ACKS and NAKS ..................................................................................... 347
8.8.4 More on Arbitration and Clock Synchronization .......................................... 347
8.8.5 I2C Addressing .............................................................................................. 351
8.8.6 Some I2C Firmware ....................................................................................... 352
8.8.7 The AVR Master I2C Code ............................................................................ 352
8.8.8 The AVR I2C Master-Receiver Mode Code .................................................. 358
8.8.9 The PIC I2C Slave-Transmitter Mode Code ................................................. 359
8.8.10 The AVR-to-PIC I2C Communications Ball ................................................. 365
8.9 Communication Options ............................................................................................ 378
8.9.1 The Serial Peripheral Interface Port .............................................................. 378
8.9.2 The Controller Area Network ....................................................................... 380
8.9.3 Acceptance Filters ......................................................................................... 386
Endnote ............................................................................................................................. 387
Chapter 9: Interfacing to Sensors and Actuators .................................................................... 389
9.1 Introduction ............................................................................................................... 389
9.2 Digital Interfacing ..................................................................................................... 389
9.2.1 Mixing 3.3 and 5 V Devices ......................................................................... 389
9.2.2 Protecting Digital Inputs ............................................................................... 392
9.2.3 Expanding Digital Inputs .............................................................................. 398
9.2.4 Expanding Digital Outputs ............................................................................ 402
9.3 High-Current Outputs ................................................................................................ 404
9.3.1 BJT-Based Drivers ........................................................................................ 405
9.3.2 MOSFETs ..................................................................................................... 409
9.3.3 Electromechanical Relays ............................................................................. 411
9.3.4 Solid-State Relays ......................................................................................... 417
9.4 CPLDs and FPGAs .................................................................................................... 418
9.5 Analog Interfacing: An Overview ............................................................................. 420
9.5.1 ADCs ............................................................................................................. 420
9.5.2 Project 1: Characterizing an Analog Channel ............................................... 421
9.6 Conclusion ................................................................................................................. 434
Endnote ............................................................................................................................. 435
Chapter 10: Other Useful Hardware Design Tips and Techniques ......................................... 437
10.1 Introduction ............................................................................................................. 437
10.2 Diagnostics .............................................................................................................. 437
10.3 Connecting Tools ..................................................................................................... 438
10.4 Other Thoughts ........................................................................................................ 439
10.5 Construction Methods ............................................................................................. 440
10.5.1 Power and Ground Planes ............................................................................ 441
10.5.2 Ground Problems ......................................................................................... 441
10.6 Electromagnetic Compatibility ............................................................................. 442
10.7 Electrostatic Discharge Effects ............................................................................. 442
10.7.1 Fault Tolerance .......................................................................................... 443
10.8 Hardware Development Tools ............................................................................... 444
10.8.1 Instrumentation Issues ............................................................................... 445
10.9 Software Development Tools ................................................................................ 445
10.10 Other Specialized Design Considerations ............................................................. 446
10.10.1 Thermal Analysis and Design ................................................................. 446
10.10.2 Battery-Powered System Design Considerations .................................... 447
10.11 Processor Performance Metrics ............................................................................. 448
10.11.1 IPS ........................................................................................................... 448
10.11.2 OPS .......................................................................................................... 448
10.11.3 Benchmarks ............................................................................................. 449
Appendix A: Schematic Symbols ........................................................................................... 451
Appendix B: Acronyms and Abbreviations ............................................................................ 459
Appendix C: PC Board Design Issues .................................................................................... 469
C.1 Introduction ............................................................................................................. 469
C.2 Resistance of Conductors ....................................................................................... 470
C.3 Voltage Drop in Signal Leads—“Kelvin” Feedback .............................................. 471
C.4 Signal Return Currents ........................................................................................... 472
C.5 Grounding in Mixed Analog/Digital Systems ........................................................ 474
C.6 Ground and Power Planes ....................................................................................... 475
C.7 Double-Sided versus Multilayer Printed Circuit Boards ........................................ 477
C.8 Multicard Mixed-Signal Systems ........................................................................... 478
C.9 Separating Analog and Digital Grounds ................................................................. 479
C.10 Grounding and Decoupling Mixed-Signal ICs with Low Digital Currents ............ 480
C.11 Treat the ADC Digital Outputs with Care .............................................................. 481
C.12 Sampling Clock Considerations ............................................................................. 483
C.13 The Origins of the Confusion About Mixed-Signal Grounding: Applying
Single-Card Grounding Concepts to Multicard Systems ........................................485
C.14 Summary: Grounding Mixed-Signal Devices with Low Digital Currents in a
Multicard System ...................................................................................................486
C.15 Summary: Grounding Mixed-Signal Devices with High Digital
Currents in a Multicard System ..............................................................................487
C.16 Grounding DSPs with Internal Phase-Locked Loops ............................................. 487
C.17 Grounding Summary .............................................................................................. 488
C.18 Some General PC Board Layout Guidelines for Mixed-Signal Systems ............... 489
C.19 Skin Effect .............................................................................................................. 491
C.20 Transmission Lines ................................................................................................. 493
C.21 Be Careful with Ground Plane Breaks .................................................................... 494
C.22 Ground Isolation Techniques .................................................................................. 495
C.23 Static PCB Effects .................................................................................................. 497
C.24 Sample MINIDIP and SOIC Op Amp PCB Guard Layouts ................................... 500
C.25 Dynamic PCB Effects ............................................................................................. 502
C.26 Stray Capacitance ................................................................................................... 503
C.27 Capacitive Noise and Faraday Shields .................................................................... 504
C.28 The Floating Shield Problem .................................................................................. 506
C.29 Buffering ADCs Against Logic Noise .................................................................... 506
Endnotes ........................................................................................................................... 509
Acknowledgments ........................................................................................................... 509
Index ....................................................................................................................................... 511

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