AMD上海热招ASIC Design Engineer / Sr. ASIC Design Engineer

RecruiterAMD

DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:

- Responsible for RTL design and synthesis of part of system IP

- Run front-end integration flow (synthesis, LINT, DFT, etc.), deliver netlists with good quality. Work with RTL owner and physical design team on timing closure and report check.

- Take part in the RTL design of some system IP blocks. Learn the spec and implement in RTL. Work with verification engineer on debugging.

PREFERRED EXPERIENCE:

- Master in electronics, computer, communication or relative majors.

- Skilled in Verilog RTL design.

- Experience in synthesis, timing analysis and formal verification.

- Experience in ASIC or FPGA projects.

- Familiar with front-end EDA tools and flows.

- Fluent written and verbal English.

有兴趣的请将简历发送至maggie1.zhang@amd.com，邮件主题标明姓名和应聘职位，谢谢。