上海需要一位 资深ASIC设计师(Principle level ASIC design)

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【猎头职位：上海需要一位 资深ASIC设计师(Principle level ASIC design) 】联系人：Tina-Wei，邮箱：hr@kthr.com，微信也可查询职位啦！打开手机微信，搜号码“KTHR_COM”或查找微信公众帐号“KT人才”或扫描以上二维码即可添加，欢迎大家关注！
Responsibility：
Module level design and verification activities including:
· Chip level or module level architecture/micro architecture definition；
· ASIC design methodology and flow development；
· Design digital control or datapath logic using Verilog HDL；
· Supervising junior engineers.


Qualification：
· BS or MS degree in EE；
· Solid understanding of digital chip design basics in terms of datapath, control, clocking, synthesis, timing etc；
· Familiar with common EDA tools in ASIC design；
· Extensive knowledge of Verilog, System Verilog, C and scripting languages；
· 10 years of experience；
· Extensive experience with networking products such as switches, network processors, home gateway, MAC, etc；
· Familiar with Ethernet technology and TCP/IP protocol.