“design a fully differential amplifier”大家看看有没有什么参考资料？

xzyan

The design specifications of the amplifier are:
Supply VDD                      5V
Dynamic range at output (DR)    >=70dB
Closed-loop gain                    2
Feedback capacitance              0.5pF
Settling accuracy               <=0.05%
Settling time ts                  <=30ns
Power consumption              as low as possible
You must design the entire circuit including the CMFB and biasing network with the exception of one independent reference current source with one terminal tied to either ground or VDD. You need to add a 3pF capacitance as a load.

有来有趣

我这里有一篇文章，你可以看看

xzyan

多谢！！^_^

lxch011

谢谢哈哈

vipwl

全差分的slew rate 和 settle time 该怎么仿真？谁有比较好的建议？

vipwl

还有CMFB环路的稳定性仿真.谁有比较好的建议。

circe

如果CMFB没有设置好，会怎么影响电路？如何确定CMFB是比较合适的？

pig

thankyou very much

pig

good paper

ph71

good thanks