【NVIDIA社招】Mask Layout Design Engineer-上海

NVHR

Hello 大家好，

这边是NVIDIA HR Tracy, 我们目前在MASK Layout Design Engineer，1年以上工作经验，欢迎投递简历到
tracyw@nvidia.com

Company introduction

http://www.nvidia.cn/object/about-nvidia-cn.html

在二十年的时间里，NVIDIA 一直在视觉计算方面 (计算机图形的艺术与科学) 勇当先锋。

凭借我们发明的 GPU ——现代视觉计算的引擎，这一领域现已扩张到涵盖了视频游戏、电影制作、产品设计、医学诊断以及科学研究等等。

现在，视觉计算正变得越来越重要，它影响着人们与科技之间的互动方式。

MASKLayout Design Engineer

JobDescription/Qualifications:
RESPONSIBILITIES
- Convert Schematic drawings to physical layout views for Standard and DataPath cells, and embedded SRAM in deep sub-micron CMOS process under Cadenceenvironment.
- Layout floor plan for both cell level and macro level.
- Layout verification including DRC(DFM)/ERC/LVS.
- Layout data base and version control, and FRAME view generation.

MINIMUM REQUIREMENTS:
- BSEE or above.
- 1 year or more relevant experience.
- Familiar with Cadence design environment.
- Experience Layout verification with Hercule/Calibre/Magma.
- Be able to estimate schedule on the assigned task.
- Basic knowledge of transistor devices.
- Unix system and commands.
- Good communication in English.
- Place and Route knowledge is a plus.

Tracy

APAC Staffing Team

QQ: 1751315121

021-61043650

sinowuwei

看一下吧