【社招】数字IC职位（上海&合肥）

FlowerSun0326

Senior IC 简历发  boss@hi-talent.com  
809955316@qq.com

Position: Senior IC Engineer（上海）

Responsibilities:

-      Independently handle key IC design tasks:

n  Block level Micro-architecture, RTL Design, Verification, Synthesis and timing closure.

n  Top level integration, including clock/reset implementation, synthesis and timing closure.

n  FPGA validation and Silicon bring-up.

-      Participating in company’s key engineering initiatives: Methodology improvement, new architecture study and proposal.

-      Coordinating joint development with 3rd party:

n  IP selection/management and vendor coordination

n  Interface with 3rd party vendor for successful execution

Requirements:

Must have:

- BSEE Degree or equivalent

- 3-5 years of experience in hands-on IC design

- Familiarity with ASIC design methodology and SoC architecture.

- Familiarity with standard CAD tools including simulation, synthesis, formal verification tools.

- Self-motivated in solving problems

- Good communication skills and fluent in English.

- Good team player.



A plus to have:

-          Good scripting skills.

-          DDR design experience.

-          Experience in DFT.

-          Experience of mobile chip development



IC验证工程师

简历发 boss@hi-talent.com

岗位职责：

Responsibilities:

Responsibilities will include developing verification environment;

developing test plans for and verifying the function of ASIC;

hands-on implementation work for every aspect of ASIC verification, working closely with the system group, architects, design and verification teams;

The successful candidate should have experience going through at least one complete and successful ASIC design/verification cycle from architecting and creating ASIC test environment to full completion of the verification work.

The candidate also needs to have a full understanding of design using Verilog and working experience with SystemVerilog. A strong communication skill in both Chinese and English is required.

任职资格的具体描述：

Qualifications:

5+ years of ASIC verification experience, complex SOC verification experience is preferred

Strong programming skills in SystemVerilog

Knowledgeable in Verilog/Verilog-PLI/SystemC/SVA/C/C++

Working Experience with UVM/OVM/VMM (at least one of them)

Responsible for implementation of verification environment and generation of high quality test cases.