Design on Power-Rail ESD Clamp Circuit for 3.3V in a 130nm(Ming-Dou Ker)

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Design on Power-Rail ESD Clamp Circuit for 3.3-V
I/O Interface by Using Only 1-V/2.5-V Low-Voltage
Devices in a 130-nm CMOS Process

Ming-Dou Ker, Senior Member, IEEE, Wen-Yi Chen, and Kuo-Chun Hsu, Member, IEEE

Abstract—A new power-rail electrostatic discharge (ESD) clamp
circuit for application in 3.3-V mixed-voltage input–output (I/O)
interface is proposed and verified in a 130-nm 1-V/2.5-V CMOS
process. The devices in this power-rail ESD clamp circuit are all
1-V or 2.5-V low-voltage nMOS/pMOS devices, which are specially
designed without suffering the gate-oxide reliability issue under
3.3-V I/O interface applications. A special ESD detection circuit
realized with the low-voltage devices is designed and added in the
power-rail ESD clamp circuit to improve ESD robustness of ESD
clamp devices by substrate-triggered technique. The experimental
results verified in a 130-nm CMOS process have proven the excellent
effectiveness of this new proposed power-rail ESD clamp circuit.
Index Terms—Electrostatic discharge (ESD), ESD protection

circuit, high-voltage tolerant, power-rail ESD clamp circuit,
substrate-triggered technique.

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