Overview on ESD protection (by Ming-Dou Ker)

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Overview on ESD protection design for mixed-voltage I/O interfaces
with high-voltage-tolerant power-rail ESD clamp circuits
in low-voltage thin-oxide CMOS technology

Ming-Dou Ker

Abstract
Electrostatic discharge (ESD) protection design for mixed-voltage I/O interfaces has been one of the key challenges of system-on-achip(SOC) implementation in nanoscale CMOS processes. The on-chip ESD protection circuit for mixed-voltage I/O interfaces should
meet the gate-oxide reliability constraints and prevent the undesired leakage current paths. This paper presents an overview on the design concept and circuit implementations of ESD protection designs for mixed-voltage I/O interfaces with only low-voltage thin-oxide CMOS transistors. Especially, the ESD protection designs for mixed-voltage I/O interfaces with ESD bus and high-voltage-tolerant power-rail ESD clamp circuits are presented and discussed.

2006 Elsevier Ltd. All rights reserved.

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