ASIC DFT PR

jj_seu

ASIC DFT Engineer        Sr. P & R engineer        Senior Digital Design Engineer        IP ASIC

@上海
合肥
北京

简历
发
芯得 jane-jin@hi-talent.com

ASICDFT Engineer

Description:

1. Implement DFT structures (internal-scan(stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in complex SoCdesign;

2. Generating, simulation and debugging thetest patterns for ATE manufacture testing;

3. Interface with back-end physical designteam to complete timing closure for test related logic;

4. Interface with operation team to debugproduction test-vectors for wafer test and final test.

Qualification:

1. BS or MS, major in EE or relateddiscipline;

2. Strong experience in ASIC logic designand verification;

3. 1+ years work experience in ASIC DFTdesign;

4. Logical thinking and sensitive to theproblem with good self-study and problem shooting ability;

5. Good communication capability andteamwork spirit.

Sr.P & R engineer

Description:

1. Responsible for the development andsupport of customer based design form netlist to GDS tape out;

2. Responsible for VLSI chip floor plan;

3. Responsible for CTS, Power plan,Placement & Routing, SPF extraction;

4. Responsible for whole chip DRC/LVS, andGDS tape out.

Qualification:

1. 3+ years of experience and minimum of BSin EE or equivalent; MS is a plus. Experienced in one of the major P&R(Place & Route) tool suites (Cadence, Synopsys, Mentor, or Magma);

2. Background in timing closure and signoff(PrimeTime experience);

3. Scripting expertise (Perl, Tcl, orPython) a strong plus;

4. Actual chip tapeout experience on arecent technology node (65nm or below) a strong plus.

SeniorDigital Design Engineer

Job Requirements:

1. At least 3 or more years of RTL leveldigital design experience with MS in EE or related (more senior levels willalso be considered)

2. Willing to work as an active team playerwith group’s goal in mind.

3. Experience in writing simple digitalmodels or real number models for analog IPs

4. Knowledge with process and devicephysics is a plus

5. Acceptable communication skill inwritten and spoken English

Job Descriptions:

1. Provide digital design support tocomplete mixed signal IP.

2. Perform mixed-signal co-simulations toensure accurate block level functionality with integrated analog circuits.

3. Logic Synthesis, Static Timing Analysisand Logic Equivalency Checking

4. Design for test, scan insertion, ATPG,Functional Test Vectors

5. Interface with Place and RouteEngineering to perform timing check and back-annotated simulations.

6. Ensure database integrity before anyrelease.

7. Execute any project assignment in thetiming manner.

8. Follow company’s quality standardsduring any project execution.

IP  ASIC

Description:

1. Understanding customer's system leveldesign and IP requirements, and survey IP vendors for the best suitable IPsolution;

2. Support customer IP related inquiry, andcontact both domestic and foreign IP vendors for support;

3. Managing internal IP project, supportinternal project IP and debugging need.

Requirement:

1. EE Bachelor degree, Master degreepreferred;

2. 5 or more years experience;

3. Strong English/Chinese verbal/writingcommunication skill;

4. Strong system level knowledge in bothdigital and analog design;

5. Strong semiconductor process relatedknowledge.

BestRegards

Jane.Jin 金娟

PrincipalConsultant & General Manager @ Hi-Talent Consulting Co.,Ltd.

上海芯得企业管理咨询有限公司

上海芯相会企业管理咨询有限公司

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E-Mail:         Jane-Jin@hi-talent.com

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