【AMD热招】上海Senior/MTS ASIC Design Verification engineer (Grahpics IP)

RecruiterAMD

AMD上海研发中心热招 Senior/MTS ASIC Design Verification engineer (Grahpics IP)，请感兴趣的把简历发送至
nina.zhang@amd.com; 并注明“所应聘职位_姓名_学历_工作年限”，谢谢。

Job Responsibilities:
- Participate graphics IP block-level verification work
- define verification plan, develop testbench, write/debug tests, analyzecoverage report to achieve verification closure
- co-work with design team for architecture discussion and RTL debug
- support IP level verification team

Preferred Experience:
- Major in EE & CS
- Be proficient in C/C++/SystemVerilog experience

- know the whole flow of verification
- Should be familiar with shell/perl/tcl programming in linux OS.
- Will be a plus if having Verilog coding, debugging and modeling experience
- Will be a big plus if having OVM/UVM experience