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Job titles:
Design Manager on PLL System
Job description:
RFIC design mainly on PLL System:
- Managing a PLL design team and developing PLL design competency.
- Responsible for mentoring junior engineers and providing recommendations on design, layout and test methodologies.
- Plan, analyze, design, simulate, verify, document and release to production PLLs for wireless applications.
- Integer/Fractional PLL system simulation, design and development.
- Assist in development of production test.
Job Requirements:
Person Specification:
- MSEE or PhD in EE, plus at least 5 years of hands-on PLL design experience with a good track record.
- In-depth understanding of phase noise mechanism in a PLL system, sigma-delta theory.
- Experience in spur compensation, current matching, integrated LPF technique, noise shaping etc. is necessary.
- Previous experiences in WCDMA, GSM/GPRS cellular, 802.11x WLAN, Bluetooth and PHS are plus.
- Strong RFIC design skills, hands-on testing and diagnostics-related RF measurement experience and familiarity with CAD tools including Cadence Spectre, SpectreRF, Virtuso, ADS, Matlab, etc. - Outstanding leadership and communication skills.
- Self-motivated attitude and excellent team spirit.
- Strong problem solving skills.
- Fluent English communications |
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