Verilog大牛请戳进来看一下

砂胆源

电路图

时序逻辑图

verilog小白一个，老师要求把RR-FSM的电路用代码写出来并综合，改了多次还是没改对，请问有没有大牛写过这个代码发发来看看      checker用的是奇偶校验     下面的是我的代码  就是不知道奇偶校验码k怎么产生  而且综合不了

`timescale 1ns/1ps
module fsm_example (din,rst_n,clk,
vout);
input din, rst_n, clk;
output vout;
reg vout,q,R3;
reg[1:0] R1,R2,R0;
reg[0:0] k;
reg[2:0] a;
reg [1:0]  next_state,current_state;
parameter [1:0] NONE = 2'b00;
parameter [1:0] SINGLE = 2'b01;
parameter [1:0] DOUBLE = 2'b11;


always @ (posedge clk or negedge rst_n)
if (!rst_n)
  begin
current_state <= NONE;
end
else
begin
R0<= next_state;R1<=R0;
R3<=q;   R2<=R1;
end
always@(R0)begin
a={R0[1:0],k[0:0]};q=^a;end
always@(posedge clk or  R0 )
if(R3)
  current_state<=R2;
else
  current_state<=R0;
  always @ (din or current_state)
case (current_state)
NONE:
if (din )
next_state = SINGLE;
else
next_state = current_state;
SINGLE:
if (din )
next_state = DOUBLE;
else
next_state = NONE;
DOUBLE:
if (din )
next_state = current_state;
else
next_state = NONE;
default:
next_state = current_state;
endcase


always @ (current_state)
case (current_state)
NONE : vout = 1'b0;
SINGLE : vout = 1'b0;
DOUBLE : vout = 1'b1;
default: vout = 1'b0;
endcase
endmodule