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本帖最后由 leo2leo 于 2015-5-11 23:15 编辑
求指点。本人不才,用虚拟机VMWARE+REL7 64位+IC616 base按下面帖子做了后不成功。
http://bbs.eetop.cn/thread-457458-1-1.html
-----提示如下----
[leo2leo@leo2leo 桌面]$ virtuoso&
[1] 6282
[leo2leo@leo2leo 桌面]$ WARNING: HOST <leo2leo> DOES NOT APPEAR TO BE A CADENCE SUPPORTED LINUX CONFIGURATION.
For More Info, Please Run '<cdsroot>/tools.lnx86/bin/checkSysConf' <productId>.
virtuoso: ERROR: The command /home/leo2leo/cadence/ic616/oa_v22.43.018//bin/sysname returned an error status:
unknown
virtuoso: INFO: Note that OpenAccess (OA) requires running the Configure phase.
virtuoso: See the "OpenAccess Installation and Configuration Guide" before
virtuoso: you complete the configuration step. This manual is included with
virtuoso: the Cadence product documentation.
[1]+ 退出 1 virtuoso
[leo2leo@leo2leo 桌面]$
-------------另外在终端输入lmli之后卡在这里
提示如下:
22:01:22 (cdslmd) Virtuoso_QRC_Extraction_GXL Virtuoso_QRC_Extraction_L Virtuoso_QRC_Extraction_XL
22:01:22 (cdslmd) Virtuoso_Schematic_Editor_GXL Virtuoso_Schematic_Editor_L Virtuoso_Schematic_Editor_XL
22:01:22 (cdslmd) Virtuoso_Schem_Option Virtuoso_SiI
VIRTUOSO_SPEC_DRIVEN_ENVIRO
22:01:22 (cdslmd) Virtuoso_Spectre Virtuoso_Spectre_GXL Virtuoso_Spectre_RF
22:01:22 (cdslmd) Virtuoso_Spectre_XL Virtuoso_Sprectre_GXL_MMSIM_LK Virtuoso_Turbo
22:01:22 (cdslmd) Virtuoso_Turbo_Basic Virtuoso_Visual_Analysis_XL Virtuoso_XL
22:01:22 (cdslmd) Virtuoso_XL_Basic visula_in
VITAL-XL
22:01:22 (cdslmd) vloglink
vmanager
VoltageStorm_Cell_Transistor2
22:01:22 (cdslmd) VoltageStorm_UI VXL-ALPHA
VXL-LMC-HW-IF
22:01:22 (cdslmd) VXL-SWITCH-RC
VXL-TURBO
VXL-VCW
22:01:22 (cdslmd) VXL-VET
VXL-VLS
VXL-VRA
22:01:22 (cdslmd) wedifsch
WinPlace
WireEdit
22:01:22 (cdslmd) WLAN_Simulation_Runtime X4ENC
xilCds
22:01:22 (cdslmd) xilComposerFE
xilConceptFE
xilEdif
22:01:22 (cdslmd) Xilinx_FPGA
22:01:22 (cdslmd)
22:01:22 (cdslmd) All FEATURE lines for cdslmd behave like INCREMENT lines
22:01:22 (cdslmd)
22:01:22 (cdslmd) EXTERNAL FILTERS are OFF
22:01:22 (lmgrd) cdslmd using TCP-port 45833 |
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