Cadence招聘资深前端验证/设计工程师

kengteng

Cadence招聘资深前端验证/设计工程师

Title: Lead/Senior VerificationEngineer (数字前端验证)

Location： SH/BJ

更多职位信息敬请关注Cadence公众微信平台：Cadence中国招聘

If you haveinterest, PLS send your update CV to zhangyl@cadence.com

  

Position Description:

1.Deliver/implement advanced verification solutions byutilizing Cadence’s Incisive Verification product portfolio. The engineershould be able to act as a strong team member and contributor, leading teamprojects and initiatives. Exercise judgment within generally defined practicesand policies.

Specific duties include:

1.Deep understanding on ASIC design and verification flow

2.Excellent knowledge of advanced verification methodologylike eRM/OVM/UVM/VMM

3.Familiar with Cadence’s Incisive Plan to ClosureMethodology (IPCM)

4.Proficiency in System Verilog, System C and/or e (Specman)

5.Developing and using Verification Components(eVC,OVC,UVC,VIP)

6.Developing and using assertion based verification andformal analysis methods

7.Skilled in scripting language, such as Perl,Cshell,Python,Makefile

8.Assessing the project verification requirements

Position Requirements:

Essential Qualifications:

1.BS degree with 4+ years of applicable experience, MSdegree with 2+ years of applicable experience in electrical engineering,microelectronics, comparable engineering science or solid state physics.  

2.Essential that the individual demonstrates strongcommunication, verbal and written. Requires good communication skills inEnglish.

Desirable Qualifications:

1.Will have demonstrated hands-on experience and expertisewith Cadence verification design tools or equivalent tools, flows andmethodologies required to execute a verification project.

2.Will have demonstrated successful completion of 3+verification projects as an individual contributor

3.Will have DDR project verification experience

Title: Lead/Senior Design Engineer (数字前端设计)

Location: SH/BJ

更多职位信息敬请关注Cadence公众微信平台：Cadence中国招聘

If you have interest, PLS send your update CV to zhangyl@cadence.com

Position Description:

Deliver/implement DDR/HBM IP. The engineer should be able toact as a strong team member and contributor. Exercise judgment within generallydefined practices and policies.

     

Specific duties include:

1.Proficiency in logic design, simulation, synthesis, STAand testing

2.Proficiency in Verilog and its simulation environment

3.Good knowledge of IC design

4.At least two years’ experience driving complex ICdevelopment projects, excellent communication skills and the uncanny ability toboth lead and contribute in a cooperative team environment.

  

Position Requirements:

1. Essential Qualifications: Must have BS degree with 4+years of applicable experience, MS degree with 2+ years of applicableexperience in electrical engineering, microelectronics, comparable engineeringscience or solid state physics.

2. Essential that the individual demonstrates strongcommunication, verbal and written.

Requires good communication skills in English.

Desirable Qualifications:

1.Will have demonstrated successful completion of 5+ designprojects as an individual contributor

2.Familiar with JEDEC-DDR/HBM, DFI and AMBA protocols andhave DDR project design experience

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