后端经理

jj_seu

1.   PHYSICAL DESIGN Manager

后端经理 张江 简历发 hr@hi-talent.com

2.   注意是Manager级别 简历发 HR@hi-talent.com  

RESPONSIBILITIES:

- Responsible for all aspects of physical design and implementation of Graphics processors, integrated chipsets and other ASICs targeted at the desktop, laptop, workstation, set-top box and home networking markets

- Participating in the efforts in establishing CAD and physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure

- Working on static timing analysis, power and noise analysis and back-end verification across multiple projects

MINIMUM REQUIREMENTS:

- BSEE, MSEE preferred

- Experience in large VLSI physical design implementation on 0.15u, 0.13u, 90nm, or 65nm technology

- Successful track record of delivering products to production is a must.

- Understanding of custom macro blocks such as RAMs, CAMs, high-speed IO drivers

- Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tapeout issues

- Working knowledge of deep sub-micron routing issues as they relate to power and timing

- Circuit level comprehension of time critical paths, and spice experience a plus

- Should be a power user of P&R and timing analysis CAD tools from Synopsys (Astro/PC/dc_shell/pt_shell/STAR-RC), Cadence (FE/Nanoroute), Sequence (Physical Studio) or Magma

- Proficiency using Perl, TCL, Scheme, Make scripting is preferred

Best Regards

Jane.Jin 金娟

Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.

上海芯得企业管理咨询有限公司

上海芯相会企业管理咨询有限公司

Mob:            18502155252

E-Mail:         Jane-Jin@hi-talent.com

微信：       xinde_jane

QQ:             1600548210

Weibo:          http://weibo.com/u/1716864892

webside：     www.hi-talent.cn