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AMD上海研发中心招聘Senior /Staff Verification Engineer for Ethernet IP,请感兴趣的候选人把简历以附件形式发送到nina.zhang@amd.com ,请在正文称述应聘理由与优势。 City/Town: Shanghai Country: China Responsibilities - IP verification and deployment of Ethernet IP for AMD SoC chips - Define IP verification strategy, Testplan, Testbench structure - Build/Debug Testbench/testcases with UVM/SystemVerilog to achieve verification goals. - Maintain verification environment, solve flow issues, and develop scripts to improve flow efficiency. Essential Functions: Testbench design, Coverage-driven verification, SystemVerilog, UVM, scripts Essential Requirements/Qualifications: - Proven IP / SoC Verification / Deployment Experience - Must have strong background on IP verification/deployment - Enthusiasm on technical topics - Major in EE & CS - Must be proficient in SystemVerilog/UVM coding, debugging and modeling - Deep understanding of below technical aspects would be an asset: 10GbE+ MAC/PHY IP/Subsystem verification Basic offload engines used in 10G+E, including stateless offload and other protocol offload such as VxLAN. Advanced offload engine TCP offload: TOE Storage offload: iSCSI HBA/FCoE HBA RDMA: RoCE/iWARP Security offload: IPSec Basic filtering and Classification: Unicast/multicast/broadcast, ACLs Advanced filtering and classification: flow based and L3 protocol based Data-center bridging, PFC/ETS/DCBX/QCN Device virtualization, SR-IOV/VEB/VEPA - 10GbE/40GbE/100GbE + Ethernet IP verification experience would be an asset - Ethernet HW/SW performance analysis experience would be an asset - Be familiar with ASIC verification flow - Be familiar with shell/perl/tcl programming in linux OS. - Should have strong problem solving skills - Good English hearing, speaking, reading and writing capabilities - Good communication skills - Have production tape out experience |