Cadence招聘资深模拟电路版图设计工程师

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Cadence招聘资深模拟电路版图设计工程师

Title: Senior design engineer-AMS

Location： SH

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Title: Senior design engineer-AMS

Position Description:

•Skillful capable ofphysical design of Analog and mixed signal area: Matching sense fromtransistor, Resistor and capacitor, Power and Ground coupling, Signal path fromDifferential pairs, etc

•Proficient with Cadencelayout tools specifically Virtuoso XL and Assura (Cadence 6.1 experience aplus)

•Experience in 65 nm and belowanalog CMOS layout, verification (DRC, LVS), and top integrated tapeout tofoundry

•Ability to coordinate withthe other analog IC circuit layout, ensuring robust, efficient, consistent and successful delivery of analogIC circuit layout.

•Fundamental understanding ofIC design technology and process/methodology

•Skilled in Analog IC toplevel chip assembly including floor planning and block layout

•Dedicated experience on keymacros is preferred: SerDes, High speed/high resolution Data Converters; HighSpeed PLL's; Low Noise Design;

•Hands-on experienceconducting DRC/LVS analysis and recommending appropriate solutions

•Solid understanding of ICdesign technology and process/methodology in AMS layout

  

  

Position Requirements:

1. BSEE degree with>3+ years of applicable experience in advanced analog and mixed signaldesign industry.

2. Essential that theindividual demonstrates strong communication, verbal and written, and projectmanagement skills. Requires very good communication skills in English andChinese.