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[招聘] 【nvidia】招聘Physical Design Engineer(METHODOLOGY)后端-上海

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发表于 2015-3-11 10:14:02 | 显示全部楼层 |阅读模式

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Hi All,

我们目前在上海招聘physical Design Design Engineer(METHODOLOGY, 偏向于EDA 工具开发,职位描述如下,如果有意向欢迎发送简历到
  tracyw@nvidia.com          QQ: 1751315121

收到简历,我会及时同你联系;

Company introduction
http://www.nvidia.cn/object/about-nvidia-cn.html
在二十年的时间里,NVIDIA 一直在视觉计算方面 (计算机图形的艺术与科学) 勇当先锋。
凭借我们发明的 GPU ——现代视觉计算的引擎,这一领域现已扩张到涵盖了视频游戏、电影制作、产品设计、医学诊断以及科学研究等等。
现在,视觉计算正变得越来越重要,它影响着人们与科技之间的互动方式。

JD----SR. PHYSICAL DESIGN METHODOLOGY ENGINEER
RESPONSIBILITIES
Responsible for the development of the physical design methodologies and flow automation for large and high speed semicustom chips using deep submicron processes.
This includes evaluating and helping improve third party tools, developing internal tools and solutions, and supporting the physical design implementation team.

MINIMUM REQUIREMENTS:
Ø  BSEE or BSCS, 3+ years of experience in large VLSI physical design implementation and automation and methodology.
Ø  Strong experience in programming of one of the following area: C/C++, Perl, Python.
Ø  Prior experience in timing closure, CTS, power distribution and analysis, power efficiency, RC extraction and correlation, xtalk analysis, signal EM, place and route, DRC/LVS and tapeout issues.  
Ø  Work knowledge of deep sub-micronissues.  
Ø  Should be a power user of P&R and timing analysis CAD tools from Magma (Blast, Talus), Synopsys (ICC/DC/PT/STAR-RC/Astro/PC), Cadence (SOCE), Mentor Graphics (Pinnacle/Olympus) or Atoptech.
Ø  Knowledge/Proficiency of C/C++ or any other software language is a plus.
Ø  Circuit level comprehension of time critical paths and Spice experience are a plus.

Tracy Wu
APAC Staffing Team
Mail: tracyw@nvidia.com
QQ:  1751315121
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