【NVIDIA社招】上海急招ASIC前端以及后端工程师

NVHR

一．公司简介

        NVIDIA (英伟达™)(www.nvidia.cn)公司(纳斯达克代码：NVDA)是全球视觉计算技术的行业领袖及GPU(图形处理器)的发明者。作为高性能处理器的GPU可在工作站、个人计算机、游戏机和移动设备上生成令人叹为观止的互动图形效果。公司在全球拥有超过8000名员工，总部在加利福尼亚州圣克拉拉。

工作地址：上海研发中心【上海申江路5709号（秋月路26号）矽岸国际2号楼】

二．投递方式

简历发送至HR(Yvette SHEN)邮箱:yvettes@nvidia.com；

三．职位详情

ASICPhysical Design engineer
As asenior member of our ASIC-PD team, you'll be working on streamlining the chipinfrastructure process across product designs, focusing on full chip layoutplanning (partitioning, planning clock distribution and other structure,methodology), partition/full chip timing closure (primetime scripts, othertools, etc) and gate-level design of high-speed logic
RESPONSIBILITIES:

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Chip integration and netlist generation

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-Synthesis, Formal verification, netlist qualitycheck

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Work in conjunction with Place and RouteEngineers to achieve timing closure for both partition level and full chiplevel

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Develop and enhance entire timing flow fromfrontend (pre-layout) to backend (post-layout) at both chip and block level.

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Develop custom timing scripts usingtcl/primetime for clock skew analysis, special circuits such as clock dividers,core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory,TMDS, etc.

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Develop flow to physically partition andfloorplan the entire chip.

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Developscripts for performing ECO's.

MINIMUMREQUIREMENTS:

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BS or MS in Electrical Engineering or ComputerScience

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Above 3 years of relevant ASIC experienceideally with a focus in the chip integration /synthesis/formal and timingclosure

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- Excellent scripts skills

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- Excellent written and verbal communicationskills in English

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- Ability to multiplex many issues, setpriorities, and work in a team environment

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- Keep up to date with leading edge technologies

ASICVerification Engineer

JobDescription/Qualifications:

RESPONSIBILITIES:

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RTL verification for various control logic andclocking logic  in GPU/tegra chips.

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Develop and maintain verification environment atboth full chip & unit level

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Code/functional coverage analysis

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Responsible for running both RTL & gatelevel simulation

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Develop testing and regression methodologies

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Develop/maintain/enhance environmenttools/scripts/makefiles

MINIMUMREQUIREMENTS:

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BSEE/MSEE/BSCS/MSCS with 3+/5+ years ofexperience in ASIC  verification

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Proficient in Verilog HDL

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Familiar with logic simulators and debug tools(VCS, NCSIM, Verdi and etc.)

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Working knowledge in C/C++, Makefile

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Must have strong programming skills in one ormore scripting languages: TCL, Perl, Python

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Knowledge/experience in one of the below areasis a big plus

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+ UVM/VMM experience

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+ ARM based SoC verification experience PCIE/USBverification experience

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+ CPU verification experience Clockingverification experience

NVHR

【NVIDIA社招】上海急招ASIC前端以及后端工程师

NVHR

【NVIDIA社招】上海急招ASIC前端以及后端工程师

NVHR

【NVIDIA社招】上海急招ASIC前端以及后端工程师