Cadence招聘资深模拟电路版图设计工程师

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Cadence招聘资深模拟电路版图设计工程师

Title: Seniordesign engineer-AMS

Location： SH

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Title: Senior designengineer-AMS

Position Description:

•Skillful capable of physical design of Analog and mixedsignal area: Matching sense from transistor, Resistor and capacitor, Power andGround coupling, Signal path from Differential pairs, etc

•Proficientwith Cadence layout tools specifically Virtuoso XL and Assura (Cadence 6.1experience a plus)

•Experiencein 65 nm and below analog CMOS layout, verification (DRC, LVS), and topintegrated tapeout to foundry

•Abilityto coordinate with the other analog IC circuit layout,  ensuring robust, efficient, consistent andsuccessful delivery of analog IC circuit layout.

•Fundamentalunderstanding of IC design technology and process/methodology

•Skilledin Analog IC top level chip assembly including floorplanning and block layout

•Dedicatedexperience on key macros is prefered: SerDes, High speed/high resolution DataConverters; High Speed PLL's; Low Noise Design;

•Hands-onexperience conducting DRC/LVS analysis and recommending appropriate solutions

•Solidunderstanding of IC design technology and process/methodology in AMS layout

  

  

PositionRequirements:

1. BSEE degree with >3+ years of applicable experience inadvanced analog and mixed signal design industry.

2. Essential that the individual demonstrates strongcommunication, verbal and written, and project management skills. Requires verygood communication skills in English and Chinese.

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