【NVIDIA]】上海招聘ASIC Physical l Design Engineer（时序分析，综合）工程师

NVHR

Hello All,

大家好，这边是NVIDIA HR Tracy, 我们目前在上海招聘ASIC Physical Design Engineer的岗位，2年以上工作经验，职位偏重于综合 时序分析方向，职位描述如下，如有意向，欢迎发送简历到 tracyw@nvidia.com  qq：1751315121 收到简历之后，我将同您联系；

在二十年的时间里，NVIDIA 一直在视觉计算方面 (计算机图形的艺术与科学) 勇当先锋。 凭借我们发明的 GPU ——现代视觉计算的引擎，这一领域现已扩张到涵盖了视频游戏、电影制作、产品设计、医学诊断以及科学研究等等。 现在，视觉计算正变得越来越重要，它影响着人们与科技之间的互动方式。

Company Description：
http://www.nvidia.cn/object/about-nvidia-cn.html

GPU ASIC Physical Design Engineer
As a senior member of our ASIC-PD team, you'll be working on streamlining the chip infrastructure process across product designs, focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology), partition/full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logic.

RESPONSIBILITIES:
Chip integration and netlist generation.
-Synthesis, Formal verification, netlist quality check.
Work in conjunction with Place and Route Engineers to achieve timing closure for both partition level and full chip level.
Develop and enhance entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.
Develop flow to physically partition and floorplan the entire chip.
Develop scripts for performing ECO's.

MINIMUM REQUIREMENTS:
BS or MS in Electrical Engineering or Computer Science
Above 3 years of relevant ASIC experience ideally with a focus in the chip integration /synthesis/formal and timing closure
- Excellent scripts skills
- Excellent written and verbal communication skills in English
- Ability to multiplex many issues, set priorities, and work in a team environment
- Keep up to date with leading edge technologies

Best Regards

Tracy WU