NVIDIA(英伟达)上海北京硬件软件类社招岗位

NVHR

NVIDIA(英伟达)上海北京硬件软件类社招岗位

一．公司简介

       NVIDIA (英伟达™)(www.nvidia.cn)公司(纳斯达克代码：NVDA)是全球视觉计算技术的行业领袖及GPU(图形处理器)的发明者。作为高性能处理器的GPU可在工作站、个人计算机、游戏机和移动设备上生成令人叹为观止的互动图形效果。公司在全球拥有超过8000名员工，总部在加利福尼亚州圣克拉拉。

工作地址：上海研发中心【上海申江路5709号（秋月路26号）矽岸国际2号楼】

二．投递方式

简历发送至HR(Yvette)邮箱:yvettes@nvidia.com；请注明投递岗位。收到简历后通过简历筛选的三个工作日内会给予回复。

ContactInfo：

QQ:1992457940

Tel:+ (86 21) 61043660

三．招聘岗位

1.Power MethodologyEngineer(Shanghai)

2.Senior Verification Engineer (Shanghai)

3.Graphics Tools Software Engineer(Shanghai)

4.System Software Engineering(Beijing)

5.ASIC Physical Design engineer(Shanghai)

四：职位详情

Job Description:

1. Power Methodology Engineer

Power methodology team is responsible forresearching power expenditures and workload efficiency to identifyarchitectural, micro-architectural strategies to improve power efficiency ofthe next generation GPU and TEGRA chips.

Responsibilities:

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Develop the power flow to automate the power expenditures measurement.

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Evaluate new low-power technologies and provide feedback to power ARCHteam to improve chip power efficiency on architectural level.

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Support GPU/TEGRA RTL designers using the power flow to do the powerscrubbing work and improve their power efficiency on micro-arch level.

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Understand and perform block level and chip-level power analysis.

Requirements:

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Familiar with advanced low power techniques and high speed clockingdesired.

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Experience in low power ASIC design/verification.

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Programming languages: Strong Verilog (or VHDL), Perl, Tcl is must, C ++is a plus.

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Tool Familiarity: PTPX, Synopsys Design Compiler, VCS simulation tool ismust, Power Artist is a plus.

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Excellent communication skills and ability to be good at teamwork.

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Excellent English writing/speaking skills.

2. Senior Verification Engineer

Responsibilities:

The Sr. verification engineer is expected tocover testbench setup, familiar with verif flow and tracking strategy.

Minimum Requirement:

- BS/MS in electrical/computer engineering andrelated.

- 3+ years MS or 5+ years BS

- Excellent perl/C++ skills

- Complex TB setup experience.

- Fully experienced verification flow,including testplan, test, coverage model, testbench, BFM modeling.

- Good understanding in Verilog and projecttree infrastructure.

- Makefile is big plus

- Fluent English (both written and spoken) andexcellent communication skills

- Demonstrated ability to work independently aswell as in a multi-disciplinary group environment

3.      Graphics Tools Software Engineer

Description/

Qualifications:   TheNVIDIA Developer Tools team is seeking a senior software developer to join oureffort to advance the state of GPU performance analysis and tuning. Thesuccessful candidate will apply knowledge of graphics programming models, GPUcompute, and GPU architecture to create tools that provide actionable feedbackto graphics and GPU compute developers. The developer should be comfortabledeveloping and debugging C/C++ application and driver code, and writinggraphics and compute tests to investigate and verify GPU performance metrics.

RESPONSIBILITIES

- Work with tools, architecture and driverteams to design, implement, and verify new performance metrics and collectionmethods for desktop GPUs and Tegra processors.

- Develop new GPU tools for Tegra SoC runningAndroid, Linux, and other embedded operating systems.

MINIMUM REQUIREMENTS

- BSEE/CS or equivalent with 3+ years ofexperience.

- Strong programming ability in C, C++, andscripting languages.

- Proficiency in Windows and/or Linuxdevelopment environments.

- Knowledge of OpenGL, OpenGL ES, DirectX,and/or CUDA is highly desirable.

- Knowledge of embedded environments such asembedded Linux, Android or QNX is highly desirable.

4. SystemSoftware Engineering

Location:Beijing

JobDescription/Qualifications:

Thehired applicant would work with a small team to develop tools for fosteringadoption of advanced GPU physics through PhysX and APEX APIs. Products indevelopment range from stand-alone tools, to plugins for popular digitalcontent creations (DCC) tools such as Autodesk and Softimage products. Thehired applicant would interact with other divisions within the company andemployees around the world to enable successful cross-functional initiatives.

Previousexperience with Autodesk (3DS Max or Maya) or Softimage product SDKs andscripting languages is a plus but not required. Applicant should be able todesign, implement, support, and document the tools.

MinimumRequirements:

- Thecandidate should be experienced with 3D graphics.

- Thecandidate should be experienced C/C++, and OpenGL or DirectX.

- Thecandidate should be familiar with Human Interface Designs.

- Musthave a solid engineering expertise: Pattern Design, OOP.

- It isa plus if with the background in Game industry.

- It isa plus if with the background in Plugin development for 3ds Max and/or Maya.

- 2+years of experience and have a BS or better.

- Anycandidate should be comfortable working in a team, be a great communicator, andhave the skills to help us deliver high quality software on a schedule.

Responsibilities:

-Design, implement, support and document tools.

- Maintain previous Plugin releases.

5.ASIC Physical Design engineer

As a senior member of our ASIC-PD team, you'll be working on streamlining thechip infrastructure process across product designs, focusing on full chiplayout planning (partitioning, planning clock distribution and other structure,methodology), partition/full chip timing closure (primetime scripts, othertools, etc) and gate-level design of high-speed logic

RESPONSIBILITIES:

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Chipintegration and netlist generation

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-Synthesis,Formal verification, netlist quality check

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Workin conjunction with Place and Route Engineers to achieve timing closure forboth partition level and full chip level

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Developand enhance entire timing flow from frontend (pre-layout) to backend(post-layout) at both chip and block level.

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Developcustom timing scripts using tcl/primetime for clock skew analysis, specialcircuits such as clock dividers, core logic <-> IO macros interfaces suchas PCI-E, Frame-Buffer/Memory, TMDS, etc.

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Developflow to physically partition and floorplan the entire chip.

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Develop scripts for performing ECO's.

MINIMUM REQUIREMENTS:

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BSor MS in Electrical Engineering or Computer Science

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Above3 years of relevant ASIC experience ideally with a focus in the chipintegration /synthesis/formal and timing closure

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-Excellent scripts skills

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-Excellent written and verbal communication skills in English

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-Ability to multiplex many issues, set priorities, and work in a teamenvironment

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-Keep up to date with leading edge technologies