资深数字IC设计工程师-上海 昆山

猎头-carry

资深数字IC设计工程师-上海 昆山

Position Responsibilities:
1. RTL level coding according to the requirement from analog/system designer;
    2. Develop and execute simulation and lab verification plan;
    3. Participate in the FPGA platform development and lab debugging;
4. Synthesize RTL code and Place&Route layout automatically.
Position Requirements:
1. MS degree in EE/CE;
    2. Good knowledge of RTL design and simulation;
    3. Able to write C code to model RTL blocks for simulation and verification;
    4. Able to write reusable Verilog RTL codes, follow design and DFT guidelines;
    5. Able to run synthesis, static timing analysis and formal verification is
highly desirable, but not required;
    6. Experience in Cadence IC Place&Route Layout tool set;
7. 5-8 years of digital design experience;
  8. Good English reading skills.
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我的QQ：2860394305
电话：0755-66606920
有意者简历可发：carry.wang@yaxunhr.com