IC Design Verification Engineer

biaowangle

Job Title: Design Verification Engineer

Job Description: Responsibility:
We are currently looking for Staff Engineers who will be responsible for all aspects of verification on next generation integrated interconnection fabric including IO Virtualization, PCIe, Ethernet that is deployed in CPU. The verification work includes developing testbenches, modeling, assertions/checkers/monitors, test plan & test development, regressions, and infrastructure development. Responsibility includes participating in the pre-silicon blocks, chip, multi-chip and system level verification strategy:

- Verification of SoC level design using random methodologies – Test Planning, Implementation and Execution.
- Develop System Verilog (OVM) random sequences and methods.
- Maintain and Interface with existing random generators, models and APIs
- Integration of random modules to various testbenches.
- Executing verification through directed and random tests for its functionality and interface protocols and tracking bug reports. Creation of the needed test libraries, test API, simulation models. Debugging regression failures and identify the cause.
- Strong documentation and communication skills.
- Ability to work well in a dynamic, fast-paced, pressure filled, across multiple sites North America and Asia
- Flexible in terms of responsibilities and hours.

Requirement:
- 5+ years experience with Master degree or 7+ years experience with Bachelor degree.
- Complex IP/ASIC/SOC Design Verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT, USB, DDR, DisplayPort, Ethernet) or multimedia/video is preferred.
- Good knowledge of SystemVerilog and OVM/UVM.
- Good knowledge of Verilog/C/C++/System C is a plus.
- Verification insights into random techniques.
- Verification of large scale ASICs.
- Experience in power verification is an asset.
- Verification of Virtualization Components is an asset.
- Strong C and C++ software development and scripting languages (Perl, C Shell, Makefile, …) experience.
- Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA).
. Be good at English communication.



If you hava interest in this position . Please contact me .
Stone Song
QQ:2632571776
Tel: 021-63511401-812
M.P: 18621601989
Email: sxd@yiri-intl.com