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Cadence SH/BJ招聘Senior Design Engineer-front-end 工作地点:上海/北京 更多职位信息敬请关注Cadence公众微信平台:Cadence中国招聘
If you have interest, PLS send your update CV to zhangyl@cadence.com Title: Senior design engineer
Position Description: •In charge of IP andSOC logic design, verification and Implementation. •Daily dutiesinclude: Digital IC micro-architecture, RTL coding, Logic Synthesis, FunctionVerification, DFT, and Static Timing Analysis. •HDL languageKnowledge, like verilog or vhdl is necessary. •C/C++/perl/tcl/csh/python,UNIX, Linux experience are plus. •Excellent analyticaland problem-solving skills. Quick learner-able to learn and apply technical andcomplex topics. •Excellentcommunication skills and the uncanny ability in a cooperative team environmentare required. •Self-motivated,result-oriented, can take ownership and follow-through on tasks. Position Requirements: Essential Qualifications: •Master degree or above •Major inMicro-electronics, Electronic Engineering, Computer Science, InformationTechnology or equivalent •Ability to workeffectively alone or as well as in the team. •Essential that theindividual demonstrates strong communication, verbal and written •Requires goodcommunication skills in English. Desirable Qualifications: •Good at anyfollowing skill sets: ASIC design, FPGA design, Computer architecture, SOCdesign based on ARM/MIPS. •Experience of DDR |