[全职] Synopsys武汉 IP Center 热招ASIC Verification Engineer

Domiliu

If you have any interest in the position, please send your bilingual resume as attachments to
dmliu@synopsys.com

1、社招：

A\ Job Title: Digital IP Designer ( ASIC Design or Verification_
USB DDR MIPI SATA)

Location: Wuhan

Job responsibilities include understanding connectivity protocols like SATA, MIPI, SDMMC, AMBA, HDMI and working on the design/directed verification of designs in such protocols.

Be able to implement test benches and test cases in HDL like Verilog is needed.

Requirements:

- Has BSEE in EE with 3+ years of relevant experience or MS with 1+ years of relevant experience in one or more of the following areas:

- Has good background in RTL design and directed verification. Hands on experience with Verilog coding and Simulation tools

-Prior ASIC/IP directed verification skills with essential knowledge of Verilog/ System Verilog

-Synthesis flow and static timing flows, Formal checking, etc is a must for candidates with design background

http://search.51job.com/job/53774338,c.html

B\ Synopsys DDR PHY CAE

Location: Shanghai/Shenzhen

Description

As a Corporate Applications Engineer (CAE) team in the Solutions Group at Synopsys, you will be responsible for technical support of customers using Synopsys DesignWare DDRn IP. You will analyze and resolve complex IP usage issues and provide timely, accurate technical guidance to customers.

http://search.51job.com/job/62297691,c.html

QQ: 1552937745

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顶一个！！！！！