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DESCRIPTION OF DUTIES IN ADDITION TO THOSE IN JOB DESCRIPTION:
- Work with RTL designer on DUT verification
- Work with RTL designer on testplan development to achieve high code coverage and functional coverage
- Build up simulation model
- Testcase development and debugging
PREFERRED EXPERIENCE:
- Bachelor with 5+ yeas and Master with 3+ in Electrical or Computer Engineering.
-Advanced Constrained-random functional verification methodology such as OVM/UVM/VMM and/or SV Assertion.
- Familiar with Linux Environment (including shell scripting and linux gnu tools)
- Good at C/C++, Perl, Makefile, familiar with, SystemVerilog, SystemC is a plus
- Familiar with RTL coding and front-end design flow
- Good communication skills and fluent English.
- Strong responsibilities and team spirit. |
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发表于 2014-8-11 11:45:14
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