Synopsys武汉 IP Center热招 ASIC/ Analog Design Engineer

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[全职]  Synopsys武汉
IP Center热招asic/ Analog Design Engineer

Synopsys is looking for ASIC/Analog engineers in Wuhan,if you have any interest in the position, please send your bilingual resume as attachmentsto
jobs-china@synopsys.com

Subjectof your email should be “Your Name_ AppliedPosition Title_ 武汉热招”

1. Job Title: DigitalIP Designer (ASIC Design or Verification for USB DDR MIPI SATA)

Location: Wuhan     http://search.51job.com/job/53774338,c.html

Job responsibilities:

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Include understanding connectivity protocolslike SATA, MIPI, SDMMC, AMBA, HDMI and working on the design/directedverification of designs in such protocols.

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Be able to implementtest benches and test cases in hdl like verilog is needed.

Requirements:

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Has BSEE in EE with 3+ years of relevantexperience or MS with 1+ years of relevant experience in one or more of thefollowing areas:

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Has good background inRTL design and directed verification. Hands on experience with Verilog codingand Simulation tools

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Prior ASIC/IP directedverification skills with essential knowledge of Verilog/ System Verilog

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Synthesis flow andstatic timing flows, Formal checking, etc is a must for candidates with designbackground

2. Job Title: Mix-signal IP Designer (Digital Design or Verification for  SerDes/ DDR PHY)

Location: Wuhan

Job Responsibilities:

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Develop and executeverification for IP level functional features related to DDR memory system.

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Work closely withDesign/Macro teams to identify the milestones and quality metrics of theproject that includes scoping, tracking and delivery.

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Participate in testenvironment infra and regression infra development, testbench development inVMM/SystemVerilog/C++, test cases development and debug.

Requirements

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Must have BSEE in EEwith 5+ years of relevant experience or MSEE with 3+years of relevant experience in the following areas:

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Verificationexperience of IP core or ASIC Design for DDR memory system or mix-signalsystem.

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Hands on experiencewith creating test plan and test environment from Functional Specifications/Test Environment Specifications with verification methodology of VMM/UVM.

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Hands on experiencewith System Verilog/ VERA coding and Simulation tools; Knowledge of C++/ OOPsConcepts.

3.  Job Title: Analog Design/layout Engineer

Location: Wuhan       http://searc h.51job.com/job/55817591,c.html

Job Responsibilities:

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Design Engineer willbe a part of a team developing high speed analog integrated circuits andresponsible for designing innovative analog, RF and mixed-signal integratedcircuits; developing circuit specifications working from published protocolsand standards; and, selecting/creating circuit architectures based on practicalexperience and knowledge of current circuit literature.

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Analog Layout isresponsible for layout design of innovative analog, RF and mixed-signalintegrated circuits;

Requirements:

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BSc in Electrical orComputer Engineering with 5+ years of experience, or MSc with 3+ years of experience,or PhD with 1+ years of experience.

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The successfulcandidate must possess a solid understanding of specialization area plusworking knowledge of one other related area;

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Has the ability toresolve issues in creative ways; execute projects from start to completion;determines and develops recommendations to solutions.

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Layout Engineer mustbe experienced with physical layout and verification tools such as Virtuso ,Laker, Calibre, Hercules and have layout design experience for advanced processnode like 40nm, 28nm.

synopsysHR

Synopsys公司在武汉光谷建立的全新的研发中心急需招募大量优质人才从事IP产品的开发