Synopsys HR 急招 IP CAE/Backend/FPGA Engineer_上海/武汉/北京

Domiliu

If you have any interest in the position, please send your bilingual resume as

attachments to
dmliu@synopsys.com

Subject of your email should be “Your Name_University_Applied Position Title_Location”

1\ Job Title:
Synopsys Backend Application Consultant (后端P&R)

Location: Shanghai

http://search.51job.com/job/55450321,c.html

Responsibilities Include

As Design Consultant working in the Physical Design team, plays a critical role in many aspects of the chip design process,

including design specification, project planning, silicon technology evaluation and selection, and physical design implementation (including netlist and timing constraint check-in, floorplanning and partitioning, top-level and block creation, physical synthesis, clock tree generation, routing, timing closure, signal integrity avoidance, analysis and repair, IR/EM analysis and physical verification).

-Design Consultant typically works as both an individual contributor or as a project leader, depending on the size and scope of the project.

-Frequent interfacing with customers and management is required.

Requirements:

-BSEE with 7-8 yr relevant experience. MSEE with 5+ yr relevant experience.

-Must have hands-on experience on 40nm or below physical design with at least 5 successful tapeouts.

-Must also demonstrate intimate knowledge of the Synopsys tools, flows and methodologies required to execute physical design projects.

These tools may include:

-Primetime SI, ICC, Star-RCXT, PrimeRail, PT-PX, Hercules/ICV and Milkyway.

- Must sustain long time international or domestic travel required by project delivery.

-Be capable to work in a stressful environment with a broad array of individuals in a cross-functional team and willing to invest extra working time and effort to keep tight project schedule.

-Own solid verbal and written English communication skills, customer interfacing skills, and business savvy.

2\  Synopsys FPGA prototyping Engineer

Location: Shanghai/Wuhan

http://search.51job.com/job/58195654,c.html

This position is responsible for IP FPGA prototype work including IP core RTL integration, test bench creation for simulation with Verification IP, FPGA synthesis to achieve clean time result, hardware testing and debugging through hardware instruments.

Position Requirements
1. BSEE or MSEE (is preferable) with 3+ yrs of experiences in FPGA design and IC validation.
2. Must be proficient with Unix OS, verilog hdl, Perl. Tcl. Shell scripting.
3. Hardware validation and debugging experiences are highly desirable.
4. Knowledge of EDA tools in the areas of Synthesis, Xilinx FPGA implementation flow, Verilog simulation and Verification is plus.
5. Knowledge one of the PCI Express/SATA/USB/HDMI/AMBA Protocol with relevant experience (specifications, compliance and interoperability testing, design/verification experience etc.) will be a definite plus.
6. Has strong desires to learn new technologies and demonstrates good analysis and problem-solving skills

3\  Synopsys FPGA Design Engineer ( SATA USB PCIE)   

Location: Shanghai/Wuhan

http://search.51job.com/job/60945310,c.html

Job Descriptions

1. This position is responsible for SATA IP FPGA prototype work including IP core RTL integration, test bench creation for simulation with Verification IP, FPGA synthesis to achieve clean time result, hardware testing and debugging through hardware instruments.

2. Will be working with the IP core, PHY Design Engineering teams and Driver software engineer to understand the IP protocols and PHY application, to define and implement the integration architecture and test plan

Position Requirements

1. BSEE or MSEE (is preferable) with 5+ yrs of experiences in FPGA design and IC validation.

2. Must be proficient with Unix OS, Verilog HDL, Perl scripting.

3. Hardware validation and debugging experiences are highly desirable.

4. Knowledge of EDA tools in the areas of Synthesis, Xilinx FPGA implementation flow, Verilog simulation and Verification is plus.

4\  Synopsys IP CAE (USB2, USB3)

Location: Beijing

http://search.51job.com/job/62182626,c.html

Description
As Corporate Applications Engineer (CAE) in the Solutions Group, you will work with a team of other dynamic and highly skilled CAEs that provide technical support to customers of Synopsys’s DesignWare USB Controller IP.
CAEs work closely with customers of DesignWare IP in different applications and pushing the envelope in different ways, through various design stages from integration to Silicon debug of their chips and ultimately contribute to customers’ success using Synopsys IP. Occasional travel will be required.

Requirements
BS, MS with 5+ years in the field of asic design.

Candidate must be highly independent with a “can-do” attitude coupled with a strong understanding and extensive experience in overall ASIC design process is required (specific experience in synthesis, STA and DFT).

Domain knowledge of the USB2 and USB3 protocols is a strong plus.

Technical background and previous experience with digital design including System/Silicon Debug experience is highly desirable.

Excellent communication skills and negotiation skills is a must.

5\  Synopsys DDR PHY CAE

Location: Shanghai

http://search.51job.com/job/62297691,c.html

Description
As a Corporate Applications Engineer (CAE) team in the Solutions Group at Synopsys, you will be responsible for technical support of customers using Synopsys DesignWare DDRn IP. You will analyze and resolve complex IP usage issues and provide timely, accurate technical guidance to customers. You will be interfacing with our Design Engineering team to report on any issues related to the IP’s design, reliability and maintenance or defects
Requirements
Qualified applicants will have a BSEE, MSEE, + 5 years relevant experience in ASIC design.
Strong communication skills and ability to interact with customers as well as peers is required.
Recent experience with ASIC implementation EDA tools and flows in the areas of Synthesis, Simulation, STA, Verification, Testability, Place and Route, Design Reuse and/or Physical Design is highly desired.
Domain knowledge of the DDR3/2 Protocols with relevant experience is a plus.
Hardware debug and troubleshooting skills are highly desirable.
Relevant experience in design, implementation or technical support with mixed signal designs is highly desired.

moonship

Signature暴漏了你的过去。。帮你顶一下！