|
马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。
您需要 登录 才可以下载或查看,没有账号?注册
x
Position Tasks, Duties and Responsibilities
The ASIC Physical Design Engineer will:
• Complete third party IP integration and ensure vendor guidelines are followed.
• Responsible for physical verification (DRC/LVS).
• IO ring design, fullchip floorplan.
• Block level implementation.
• Work with front-end engineers to resolve problems and achieve design closure.
Candidate Qualifications:
Candidate must:
• Hold BSEE (MS preferred).
• Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification
• Be able to complete block and chip level tapeout quality LVS and LVS and DRC.
• Have the ability to independently identify and resolve design, tool, and flow problems.
• Have related timing and physical concept.
• Be able to design and implement physical design strategies and methodologies for deep submicron designs.
• Familiar with EDA tools.
• Familiar with Linux environments.
Any of the following is beneficial:
• STA constraint design
• Equivalence checking – RTL to gates, and gates to gates.
KT Human Resources Consulting Company (Shanghai) was established in 2001 in response to a need for a recruitment consultancy to be an active, contributing member of the semiconductor community, as opposed to simply a supplier to it.We provide professional search and talent acquisition in the Integrated Circuit、Electronic、Telecommunications industry of international corporations in Greater China. Our client list contains numerous international companies, many of them are long-term customers.
If you interested in the job, pls sent your cv to: hr@kthr.com, thanks!
“KT人才”微信也可查询职位啦!打开手机微信,搜号码“KTHR_COM”或查找微信公众帐号“KT人才”即可添加,欢迎大家关注!(关注成功后输入”KT“即可查询职位!) |
|