马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
本帖最后由 zphcd 于 2014-6-3 09:21 编辑
大家好， 我使用 calbre2008 lvs pass, calibre2011 lvs net error ，感觉 lvs 开关选项的问题（版图，网标，lvs rule 都是相同的，好像这两个版本的默认选项不同），还请大侠多多指点，谢谢。
比较了下， calibre 2011 LVS rule 比 calibre 2008 LVS rule 多了 一个 error, 四个不同选项：
ERROR Connectivity error
LVS FLATTEN INSIDE NO
LVS SPICE SCALE X PARAMETERS NO
LVS SHORT EQUIVALENT NODES NO
LVS FILTER UNUSED OPTION AB AC AD AE RB RC RD RE ZC RG (CAL2011 没有 RG )
LVS CAL2008 与 CAL2011 REPORT
如下：
##################################################
## ##
## C A L I B R E S Y S T E M ##
## ##
## L V S R E P O R T ##
## ##
##################################################
CALIBRE VERSION: v2008.3_34.24 Fri Oct 3 15:32:40 PDT 2008
OVERALL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of instances.
Error: Property errors.
Warning: Unbalanced smashed mosfets were matched.
Warning: Ambiguity points were found and resolved arbitrarily.
**************************************************************************************************************
CELL SUMMARY
**************************************************************************************************************
Result Layout Source
----------- ----------- --------------
INCORRECT XRC9607_OTG20_PHY XRC9607_OTG20_PHY
**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************
o LVS Setup:
// LVS COMPONENT TYPE PROPERTY
// LVS COMPONENT SUBTYPE PROPERTY
// LVS PIN NAME PROPERTY
LVS POWER NAME "VDD" "SAVDD?" "?VDD?" "?VCC?" "?vcc?" "?vdd?" "AVD?" "VD*" "VRP" "VCCA?" "AVD_REF"
"AVD*" "VREFP_SAR"
LVS GROUND NAME "VSS" "SAVSS?" "?gnd?" "?GND?" "?VSS?" "?vss?" "AVS" "AGND?" "VRN" "VREFN_SAR"
LVS CELL SUPPLY NO
LVS RECOGNIZE GATES ALL
LVS IGNORE PORTS NO
LVS CHECK PORT NAMES YES
LVS IGNORE TRIVIAL NAMED PORTS NO
LVS BUILTIN DEVICE PIN SWAP YES
LVS ALL CAPACITOR PINS SWAPPABLE YES
LVS DISCARD PINS BY DEVICE NO
LVS SOFT SUBSTRATE PINS NO
LVS INJECT LOGIC NO
LVS EXPAND UNBALANCED CELLS YES
LVS EXPAND SEED PROMOTIONS NO
LVS PRESERVE PARAMETERIZED CELLS NO
LVS GLOBALS ARE PORTS YES
LVS REVERSE WL NO
LVS SPICE PREFER PINS YES
LVS SPICE SLASH IS SPACE YES
LVS SPICE ALLOW FLOATING PINS YES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGS NO
LVS SPICE CONDITIONAL LDD NO
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
LVS SPICE IMPLIED MOS AREA NO
LVS SPICE MULTIPLIER NAME "M" "MR"
LVS SPICE OVERRIDE GLOBALS NO
LVS SPICE REDEFINE PARAM NO
LVS SPICE REPLICATE DEVICES NO
LVS SPICE STRICT WL NO
// LVS SPICE OPTION
LVS STRICT SUBTYPES NO
LVS EXACT SUBTYPES NO
LAYOUT CASE NO
SOURCE CASE NO
LVS COMPARE CASE NO
LVS DOWNCASE DEVICE NO
LVS REPORT MAXIMUM ALL
LVS PROPERTY RESOLUTION MAXIMUM 65536
// LVS SIGNATURE MAXIMUM
LVS FILTER UNUSED OPTION AB AC AD AE RB RC RD RE RG ZC
// LVS REPORT OPTION
LVS REPORT UNITS YES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// Device Type Map
// Reduction
LVS REDUCE SERIES MOS YES
LVS REDUCE PARALLEL MOS YES
LVS REDUCE SEMI SERIES MOS NO
LVS REDUCE SPLIT GATES YES
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE SERIES CAPACITORS NO
LVS REDUCE PARALLEL CAPACITORS NO
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE PARALLEL RESISTORS YES
LVS REDUCE PARALLEL DIODES YES
LVS REDUCTION PRIORITY PARALLEL
// Trace Property
CELL COMPARISON RESULTS ( TOP LEVEL )
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of instances (see below).
Error: Property errors.
Warning: Unbalanced smashed mosfets were matched.
Warning: Ambiguity points were found and resolved arbitrarily.
LAYOUT CELL NAME: XRC9607_OTG20_PHY
SOURCE CELL NAME: XRC9607_OTG20_PHY
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 114 115 *
Nets: 30859 30311 *
Instances: 32781 28828 * MN (4 pins)
32110 28044 * MP (4 pins)
9 2 * Q (3 pins)
0 2 * C (2 pins)
8 4 * rppo_ckt (2 pins)
448 135 * rpposab_ckt (2 pins)
32 13 * D (2 pins)
------ ------
Total Inst: 65388 57028
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 114 114
Nets: 16804 16804
Instances: 1779 1779 MN (4 pins)
2730 2729 * MP (4 pins)
2 2 Q (3 pins)
0 2 * C (2 pins)
4 4 rppo_ckt (2 pins)
127 127 rpposab_ckt (2 pins)
12 12 D (2 pins)
10849 10849 INV (2 pins)
1528 1528 NAND2 (3 pins)
63 63 NAND3 (4 pins)
29 29 NAND4 (5 pins)
384 384 NOR2 (3 pins)
59 59 NOR3 (4 pins)
29 29 NOR4 (5 pins)
91 91 AOI_2_1 (4 pins)
80 80 AOI_2_1_1 (5 pins)
136 136 AOI_2_2 (5 pins)
5 5 AOI_2_2_1 (6 pins)
19 19 AOI_2_2_2 (7 pins)
14 14 AOI_3_1 (5 pins)
10 10 AOI_3_2 (6 pins)
155 155 OAI_2_1 (4 pins)
76 76 OAI_2_1_1 (5 pins)
79 79 OAI_2_2 (5 pins)
15 15 OAI_2_2_1 (6 pins)
2 2 OAI_2_2_2 (7 pins)
14 14 OAI_3_1 (5 pins)
12 12 OAI_3_2 (6 pins)
4 4 OAI_3_3 (7 pins)
1258 1258 SDW2 (3 pins)
2002 2002 SDW3 (4 pins)
3362 3362 SUP2 (3 pins)
52 52 SUP3 (4 pins)
74 74 SPDW_2_1 (4 pins)
1 1 SPDW_2_2_2 (7 pins)
35 35 SPUP_2_1 (4 pins)
1 1 SPUP_2_2_2 (7 pins)
62 62 SMN2 (4 pins)
1 1 SMN3 (5 pins)
4 4 SMP2 (4 pins)
2 2 SMP3 (5 pins)
33 33 SPMN((2+1)*1) (6 pins)
22 22 SPMP((2+1)*1) (6 pins)
------ ------
Total Inst: 25216 25217
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
INCORRECT INSTANCES
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
1 X0/X13/X35/M3(232.930,130.085) MP(P12LL) ** missing instance **
--------------------------------------------------------------------------------------------------------------
2 ** missing instance ** XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DM_driver/CC0 C(CP)
--------------------------------------------------------------------------------------------------------------
3 ** missing instance ** XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DP_driver/CC0 C(CP)
**************************************************************************************************************
PROPERTY ERRORS
DISC# LAYOUT SOURCE ERROR
**************************************************************************************************************
4 X0/X15/X12/X7/M39(239.712,241.822) MP(POD33LL) XI_ANA/XI_Transceiver/XI_HSRCV/XI_Amp/MPM5 MP(POD33LL)
l: 5 u l: 5.816 u 14%
w: 47.2 u w: 40.231 u 17.3%
5 X0/X13/X15/X78/M6(121.219,188.585) MN(NOD33LL) XI_ANA/XI_CLKGEN/XI_PLL/XI_LPF/MM4 MN(NOD33LL)
l: 11.9881 u l: 10.987 u 9.11%
w: 571.468 u w: 649.7 u 12%
6 X0/X14/X13/M25(186.376,547.270) MN(NOD33LL) XI_ANA/XI_VREF_OTG_HOST/XI_VREF/MM48 MN(NOD33LL)
l: 5.56485 u l: 7.019 u 20.7%
w: 58.7706 u w: 40.438 u 45.3%
7 X0/X14/X13/M37(214.906,534.875) MN(NOD33LL) XI_ANA/XI_VREF_OTG_HOST/MNcap MN(NOD33LL)
l: 5.38391 u l: 10 u 46.2%
w: 49.6665 u w: 10 u 397%
8 X0/X19/M9(256.609,96.864) MN(NOD33LL) XI_ANA/XI_CLKGEN/XI_PLL/XI_VtoI/MNM2 MN(NOD33LL)
l: 7.68706 u l: 6.668 u 15.3%
w: 118.381 u w: 141.58 u 16.4%
9 X0/X8/X29/M3(86.901,334.980) MN(NOD33LL) XI_ANA/XI_DPM/MM18 MN(NOD33LL)
l: 3.79285 u l: 4 u 5.18%
w: 26.55 u w: 25 u 6.2%
10 X0/X14/X20/M1(233.701,562.439) MN(NOD33LL) XI_ANA/XI_VREF_OTG_HOST/XI_OTGCON/MM13 MN(NOD33LL)
l: 5.05211 u l: 5 u 1.04%
w: 63.6566 u w: 60 u 6.09%
11 X0/X14/X20/X53/M34(237.186,536.596) MN(NOD33LL) XI_ANA/XI_VREF_OTG_HOST/XI_OTGCON/XI_PD_ALL/MM17 MN(NOD33LL)
l: 2.81824 u l: 5 u 43.6%
w: 71.8887 u w: 40 u 79.7%
12 X0/X15/X12/X7/M31(239.907,233.072) MN(NOD33LL) XI_ANA/XI_Transceiver/XI_HSRCV/XI_Amp/MNM7 MN(NOD33LL)
l: 5 u l: 6 u 16.7%
w: 27.2 u w: 20 u 36%
13 X0/X15/X16/M3(235.605,245.190) MN(NOD33LL) XI_ANA/MM0 MN(NOD33LL)
l: 7.68377 u l: 10 u 23.2%
w: 280.103 u w: 10 u 2.7e+03%
14 X0/X6/X18/X1/M1(36.390,72.650) MN(NOD33LL) XI_ANA/XI_ID/MM0 MN(NOD33LL)
w: 720 u w: 420 u 71.4%
15 X0/X6/X24/X1/M1(46.058,72.700) MP(POD33LL) XI_ANA/XI_ID/MM4 MP(POD33LL)
w: 672 u w: 392 u 71.4%
16 X0/X8/X29/X30/X0/M0(93.288,330.600) MP(POD33LL) XI_ANA/XI_DPM/MM13 MP(POD33LL)
l: 20 u l: 21 u 4.76%
17 X0/X9/X7/X6/D0(6.790,573.730) D(NDIO25LL) XI_ANA/XI_VBUS/DD5 D(NDIO25LL)
a: 954.245 sq u a: 905.384 sq u 5.4%
18 X0/X11/X7/D0(37.249,489.110) D(NDIO25LL) XI_ANA/XI_AGND1_AGND2/DD5 D(NDIO25LL)
a: 2052.97 sq u a: 1722.09 sq u 19.2%
19 X1/X8/X50/X1/M0(250.130,328.325) MP(P25LL) MPM0 MP(P25LL)
l: 5 u l: 0.28 u 1.69e+03%
w: 82.36 u w: 0.21 u 3.91e+04%
20 X0/X9/X6/X7/X1/X1/X1/M3(62.940,570.720) MN(NOD33LL) XI_ANA/XI_VBUS/MM10 MN(NOD33LL)
w: 960 u w: 480 u 100%
21 X0/X9/X6/X7/X1/X1/X1/M2(62.940,569.920) MN(NOD33LL) XI_ANA/XI_VBUS/MM11 MN(NOD33LL)
w: 960 u w: 480 u 100%
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 114 114 0 0
Nets: 16804 16804 0 0
Instances: 1468 1468 0 0 MN(N12LL)
311 311 0 0 MN(NOD33LL)
2522 2522 1 0 MP(P12LL)
1 1 0 0 MP(P25LL)
206 206 0 0 MP(POD33LL)
2 2 0 0 Q(PNP25A25LL_SH)
0 0 0 2 C(CP)
4 4 0 0 rppo_ckt
127 127 0 0 rpposab_ckt
4 4 0 0 D(NDIO25LL)
8 8 0 0 D(PDIO25LL)
10849 10849 0 0 INV
1528 1528 0 0 NAND2
63 63 0 0 NAND3
29 29 0 0 NAND4
384 384 0 0 NOR2
59 59 0 0 NOR3
29 29 0 0 NOR4
91 91 0 0 AOI_2_1
80 80 0 0 AOI_2_1_1
136 136 0 0 AOI_2_2
5 5 0 0 AOI_2_2_1
19 19 0 0 AOI_2_2_2
14 14 0 0 AOI_3_1
10 10 0 0 AOI_3_2
155 155 0 0 OAI_2_1
76 76 0 0 OAI_2_1_1
79 79 0 0 OAI_2_2
15 15 0 0 OAI_2_2_1
2 2 0 0 OAI_2_2_2
14 14 0 0 OAI_3_1
12 12 0 0 OAI_3_2
4 4 0 0 OAI_3_3
1258 1258 0 0 SDW2
2002 2002 0 0 SDW3
3362 3362 0 0 SUP2
52 52 0 0 SUP3
74 74 0 0 SPDW_2_1
1 1 0 0 SPDW_2_2_2
35 35 0 0 SPUP_2_1
1 1 0 0 SPUP_2_2_2
62 62 0 0 SMN2
1 1 0 0 SMN3
4 4 0 0 SMP2
2 2 0 0 SMP3
33 33 0 0 SPMN((2+1)*1)
22 22 0 0 SPMP((2+1)*1)
------- ------- --------- ---------
Total Inst: 25215 25215 1 2
——————————————————————————————————————————————————————-----------------
-----------------------------------------------------------------------------------------------------------------------------
-----------------------------------------------------------------------------------------------------------------------------
##################################################
## ##
## C A L I B R E S Y S T E M ##
## ##
## L V S R E P O R T ##
## ##
##################################################
CALIBRE VERSION: v2011.2_34.26 Wed Jul 6 05:20:09 PDT 2011
OVERALL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of instances.
Error: Connectivity errors.
Error: Property errors.
Warning: Unbalanced smashed mosfets were matched.
Warning: Ambiguity points were found and resolved arbitrarily.
**************************************************************************************************************
CELL SUMMARY
**************************************************************************************************************
Result Layout Source
----------- ----------- --------------
INCORRECT XRC9607_OTG20_PHY XRC9607_OTG20_PHY
**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************
o LVS Setup:
// LVS COMPONENT TYPE PROPERTY
// LVS COMPONENT SUBTYPE PROPERTY
// LVS PIN NAME PROPERTY
LVS POWER NAME "VDD" "SAVDD?" "?VDD?" "?VCC?" "?vcc?" "?vdd?" "AVD?" "VD*" "VRP" "VCCA?" "AVD_REF"
"AVD*" "VREFP_SAR"
LVS GROUND NAME "VSS" "SAVSS?" "?gnd?" "?GND?" "?VSS?" "?vss?" "AVS" "AGND?" "VRN" "VREFN_SAR"
LVS CELL SUPPLY NO
LVS RECOGNIZE GATES ALL
LVS IGNORE PORTS NO
LVS CHECK PORT NAMES YES
LVS IGNORE TRIVIAL NAMED PORTS NO
LVS BUILTIN DEVICE PIN SWAP YES
LVS ALL CAPACITOR PINS SWAPPABLE YES
LVS DISCARD PINS BY DEVICE NO
LVS SOFT SUBSTRATE PINS NO
LVS INJECT LOGIC NO
LVS EXPAND UNBALANCED CELLS YES
LVS FLATTEN INSIDE CELL NO
LVS EXPAND SEED PROMOTIONS NO
LVS PRESERVE PARAMETERIZED CELLS NO
LVS GLOBALS ARE PORTS YES
LVS REVERSE WL NO
LVS SPICE PREFER PINS YES
LVS SPICE SLASH IS SPACE YES
LVS SPICE ALLOW FLOATING PINS YES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGS NO
LVS SPICE CONDITIONAL LDD NO
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
LVS SPICE IMPLIED MOS AREA NO
LVS SPICE MULTIPLIER NAME "M" "MR"
LVS SPICE OVERRIDE GLOBALS NO
LVS SPICE REDEFINE PARAM NO
LVS SPICE REPLICATE DEVICES NO
LVS SPICE SCALE X PARAMETERS NO
LVS SPICE STRICT WL NO
// LVS SPICE OPTION
LVS STRICT SUBTYPES NO
LVS EXACT SUBTYPES NO
LAYOUT CASE NO
SOURCE CASE NO
LVS COMPARE CASE NO
LVS DOWNCASE DEVICE NO
LVS REPORT MAXIMUM ALL
LVS PROPERTY RESOLUTION MAXIMUM 65536
// LVS SIGNATURE MAXIMUM
LVS FILTER UNUSED OPTION AB AC AD AE RB RC RD RE ZC
// LVS REPORT OPTION
LVS REPORT UNITS YES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// Device Type Map
// Reduction
LVS REDUCE SERIES MOS YES
LVS REDUCE PARALLEL MOS YES
LVS REDUCE SEMI SERIES MOS NO
LVS REDUCE SPLIT GATES YES
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE SERIES CAPACITORS NO
LVS REDUCE PARALLEL CAPACITORS NO
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE PARALLEL RESISTORS YES
LVS REDUCE PARALLEL DIODES YES
LVS REDUCTION PRIORITY PARALLEL
LVS SHORT EQUIVALENT NODES NO
// Trace Property
CELL COMPARISON RESULTS ( TOP LEVEL )
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of instances (see below).
Error: Connectivity errors.
Error: Property errors.
Warning: Unbalanced smashed mosfets were matched.
Warning: Ambiguity points were found and resolved arbitrarily.
LAYOUT CELL NAME: XRC9607_OTG20_PHY
SOURCE CELL NAME: XRC9607_OTG20_PHY
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 114 115 *
Nets: 30859 30312 *
Instances: 32781 28828 * MN (4 pins)
32110 28044 * MP (4 pins)
9 2 * Q (3 pins)
0 2 * C (2 pins)
8 4 * rppo_ckt (2 pins)
448 135 * rpposab_ckt (2 pins)
32 13 * D (2 pins)
------ ------
Total Inst: 65388 57028
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 114 114
Nets: 16804 16804
Instances: 1779 1779 MN (4 pins)
2730 2729 * MP (4 pins)
2 2 Q (3 pins)
0 2 * C (2 pins)
4 4 rppo_ckt (2 pins)
127 127 rpposab_ckt (2 pins)
12 12 D (2 pins)
10849 10849 INV (2 pins)
1528 1528 NAND2 (3 pins)
63 63 NAND3 (4 pins)
29 29 NAND4 (5 pins)
384 384 NOR2 (3 pins)
59 59 NOR3 (4 pins)
29 29 NOR4 (5 pins)
91 91 AOI_2_1 (4 pins)
80 80 AOI_2_1_1 (5 pins)
136 136 AOI_2_2 (5 pins)
5 5 AOI_2_2_1 (6 pins)
19 19 AOI_2_2_2 (7 pins)
14 14 AOI_3_1 (5 pins)
10 10 AOI_3_2 (6 pins)
155 155 OAI_2_1 (4 pins)
76 76 OAI_2_1_1 (5 pins)
79 79 OAI_2_2 (5 pins)
15 15 OAI_2_2_1 (6 pins)
2 2 OAI_2_2_2 (7 pins)
14 14 OAI_3_1 (5 pins)
12 12 OAI_3_2 (6 pins)
4 4 OAI_3_3 (7 pins)
1258 1258 SDW2 (3 pins)
2002 2002 SDW3 (4 pins)
3362 3362 SUP2 (3 pins)
52 52 SUP3 (4 pins)
74 74 SPDW_2_1 (4 pins)
1 1 SPDW_2_2_2 (7 pins)
35 35 SPUP_2_1 (4 pins)
1 1 SPUP_2_2_2 (7 pins)
62 62 SMN2 (4 pins)
1 1 SMN3 (5 pins)
4 4 SMP2 (4 pins)
2 2 SMP3 (5 pins)
33 33 SPMN((2+1)*1) (6 pins)
22 22 SPMP((2+1)*1) (6 pins)
------ ------
Total Inst: 25216 25217
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
INCORRECT NETS
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
1 Net X0/X8/X26/X28/19 XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DM_driver/net0189
-------------------------- --------------------------
(SDW2) utput ** missing connection **
X0/X8/X26/X28/X10/X0/X1/M2(24.280,306.175):s
X0/X8/X26/X28/X10/X0/X1/X8(51.820,308.325):MINUS ** missing connection **
** missing connection ** (SDW2)utput
XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DM_driver/MM9:d
** missing connection ** XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DM_driver/XR2:MINUS
--------------------------------------------------------------------------------------------------------------
2 Net X0/X8/X26/X28/X10/16 XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DM_driver/net016
-------------------------- --------------------------
(SDW2)utput ** missing connection **
X0/X8/X26/X28/X10/X1/X1/M2(24.280,297.355):s
X0/X8/X26/X28/X10/X1/X1/X8(51.820,299.505):MINUS ** missing connection **
** missing connection ** (SDW2):output
XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DM_driver/MM1:d
** missing connection ** XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DM_driver/XR0:MINUS
--------------------------------------------------------------------------------------------------------------
3 Net X0/X8/X26/X28/X10/X1/15 XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DM_driver/net0201
-------------------------- --------------------------
(SDW2):output ** missing connection **
X0/X8/X26/X28/X10/X1/X0/M2(24.280,303.365):s
X0/X8/X26/X28/X10/X1/X0/X8(51.820,301.215):MINUS ** missing connection **
** missing connection ** (SDW2):output
XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DM_driver/MM4:d
** missing connection ** XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DM_driver/XR1:MINUS
--------------------------------------------------------------------------------------------------------------
4 Net X0/X8/X26/X28/X11/X0/15 XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DM_driver/net0442
-------------------------- --------------------------
(SDW2):output ** missing connection **
X0/X8/X26/X28/X11/X0/X0/M2(24.280,294.545):s
X0/X8/X26/X28/X11/X0/X0/X8(51.820,292.395):MINUS ** missing connection **
** missing connection ** (SDW2):output
XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DM_driver/MM21:d
** missing connection ** XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DM_driver/XR6:MINUS
--------------------------------------------------------------------------------------------------------------
5 Net X0/X8/X26/X28/X11/X1/15 XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DM_driver/net0153
-------------------------- --------------------------
(SDW2):output ** missing connection **
X0/X8/X26/X28/X11/X1/X0/M2(24.280,285.725):s
X0/X8/X26/X28/X11/X1/X0/X8(51.820,283.575):MINUS ** missing connection **
** missing connection ** (SDW2):output
XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DM_driver/MM22:d
** missing connection ** XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DM_driver/XR7:MINUS
--------------------------------------------------------------------------------------------------------------
6 Net X0/X8/X27/X28/X10/16 XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DP_driver/net016
-------------------------- --------------------------
(SDW2):output ** missing connection **
X0/X8/X27/X28/X10/X1/X1/M2(24.280,366.645):s
X0/X8/X27/X28/X10/X1/X1/X8(51.820,364.495):MINUS ** missing connection **
** missing connection ** (SDW2):output
XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DP_driver/MM1:d
** missing connection ** XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DP_driver/XR0:MINUS
--------------------------------------------------------------------------------------------------------------
7 Net X0/X8/X27/X28/X10/X1/15 XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DP_driver/net0189
-------------------------- --------------------------
X0/X8/X27/X28/X10/X1/X0/X8(51.820,362.785):MINUS ** missing connection **
** missing connection ** XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DP_driver/XR2:MINUS
--------------------------------------------------------------------------------------------------------------
8 Net X0/X8/X27/X28/X11/X0/15 XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DP_driver/net0442
-------------------------- --------------------------
(SDW2):output ** missing connection **
X0/X8/X27/X28/X11/X0/X0/M2(24.280,369.455):s
X0/X8/X27/X28/X11/X0/X0/X8(51.820,371.605):MINUS ** missing connection **
** missing connection ** (SDW2):output
XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DP_driver/MM21:d
** missing connection ** XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DP_driver/XR6:MINUS
--------------------------------------------------------------------------------------------------------------
9 Net X0/X8/X27/X28/X11/X1/15 XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DP_driver/net0153
-------------------------- --------------------------
(SDW2):output ** missing connection **
X0/X8/X27/X28/X11/X1/X0/M2(24.280,378.275):s
X0/X8/X27/X28/X11/X1/X0/X8(51.820,380.425):MINUS ** missing connection **
** missing connection ** (SDW2):output
XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DP_driver/MM22:d
** missing connection ** XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DP_driver/XR7:MINUS
--------------------------------------------------------------------------------------------------------------
10 Net X0/X8/X26/X28/X10/X0/15 ** no similar net **
--------------------------------------------------------------------------------------------------------------
11 Net X0/X8/X27/X28/X10/X0/15 ** no similar net **
--------------------------------------------------------------------------------------------------------------
12 ** no similar net ** XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DM_driver/OUT_T
--------------------------------------------------------------------------------------------------------------
13 ** no similar net ** XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DP_driver/OUT_T
**************************************************************************************************************
INCORRECT INSTANCES
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
14 X0/X13/X37/M3(232.930,130.085) MP(P12LL) ** missing instance **
--------------------------------------------------------------------------------------------------------------
15 ** missing instance ** XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DM_driver/CC0 C(CP)
--------------------------------------------------------------------------------------------------------------
16 ** missing instance ** XI_ANA/XI_DPM/XI_FLSDRV_TOP/XI_DP_driver/CC0 C(CP)
**************************************************************************************************************
PROPERTY ERRORS
DISC# LAYOUT SOURCE ERROR
**************************************************************************************************************
17 X0/X15/X16/X11/M39(239.712,241.822) MP(POD33LL) XI_ANA/XI_Transceiver/XI_HSRCV/XI_Amp/MPM5 MP(POD33LL)
l: 5 u l: 5.816 u 14%
w: 47.2 u w: 40.231 u 17.3%
18 X0/X13/X15/X78/M6(121.219,188.585) MN(NOD33LL) XI_ANA/XI_CLKGEN/XI_PLL/XI_LPF/MM4 MN(NOD33LL)
l: 11.9881 u l: 10.987 u 9.11%
w: 571.468 u w: 649.7 u 12%
19 X0/X14/X13/M25(186.376,547.270) MN(NOD33LL) XI_ANA/XI_VREF_OTG_HOST/XI_VREF/MM48 MN(NOD33LL)
l: 5.56485 u l: 7.019 u 20.7%
w: 58.7706 u w: 40.438 u 45.3%
20 X0/X14/X13/M37(214.906,534.875) MN(NOD33LL) XI_ANA/XI_VREF_OTG_HOST/MNcap MN(NOD33LL)
l: 5.38391 u l: 10 u 46.2%
w: 49.6665 u w: 10 u 397%
21 X0/X19/M9(256.609,96.864) MN(NOD33LL) XI_ANA/XI_CLKGEN/XI_PLL/XI_VtoI/MNM2 MN(NOD33LL)
l: 7.68706 u l: 6.668 u 15.3%
w: 118.381 u w: 141.58 u 16.4%
22 X0/X8/X29/M3(86.901,334.980) MN(NOD33LL) XI_ANA/XI_DPM/MM18 MN(NOD33LL)
l: 3.79285 u l: 4 u 5.18%
w: 26.55 u w: 25 u 6.2%
23 X0/X14/X20/M1(233.701,562.439) MN(NOD33LL) XI_ANA/XI_VREF_OTG_HOST/XI_OTGCON/MM13 MN(NOD33LL)
l: 5.05211 u l: 5 u 1.04%
w: 63.6566 u w: 60 u 6.09%
24 X0/X14/X20/X53/M34(237.186,536.596) MN(NOD33LL) XI_ANA/XI_VREF_OTG_HOST/XI_OTGCON/XI_PD_ALL/MM17 MN(NOD33LL)
l: 2.81824 u l: 5 u 43.6%
w: 71.8887 u w: 40 u 79.7%
25 X0/X15/X16/X11/M31(239.907,233.072) MN(NOD33LL) XI_ANA/XI_Transceiver/XI_HSRCV/XI_Amp/MNM7 MN(NOD33LL)
l: 5 u l: 6 u 16.7%
w: 27.2 u w: 20 u 36%
26 X0/X15/X20/M3(235.605,245.190) MN(NOD33LL) XI_ANA/MM0 MN(NOD33LL)
l: 7.68377 u l: 10 u 23.2%
w: 280.103 u w: 10 u 2.7e+03%
27 X0/X6/X18/X1/M1(36.390,72.650) MN(NOD33LL) XI_ANA/XI_ID/MM0 MN(NOD33LL)
w: 720 u w: 420 u 71.4%
28 X0/X6/X24/X1/M1(46.058,72.700) MP(POD33LL) XI_ANA/XI_ID/MM4 MP(POD33LL)
w: 672 u w: 392 u 71.4%
29 X0/X8/X29/X30/M0(94.018,330.600) MP(POD33LL) XI_ANA/XI_DPM/MM13 MP(POD33LL)
l: 20 u l: 21 u 4.76%
30 X0/X9/X7/X6/D0(6.790,573.730) D(NDIO25LL) XI_ANA/XI_VBUS/DD5 D(NDIO25LL)
a: 954.245 sq u a: 905.384 sq u 5.4%
31 X0/X11/X7/D0(37.249,489.110) D(NDIO25LL) XI_ANA/XI_AGND1_AGND2/DD5 D(NDIO25LL)
a: 2052.97 sq u a: 1722.09 sq u 19.2%
32 X1/X8/X50/X1/M0(250.130,328.325) MP(P25LL) MPM0 MP(P25LL)
l: 5 u l: 0.28 u 1.69e+03%
w: 82.36 u w: 0.21 u 3.91e+04%
33 X0/X9/X6/X9/X1/X1/M3(62.940,570.720) MN(NOD33LL) XI_ANA/XI_VBUS/MM10 MN(NOD33LL)
w: 960 u w: 480 u 100%
34 X0/X9/X6/X9/X1/X1/M2(62.940,569.920) MN(NOD33LL) XI_ANA/XI_VBUS/MM11 MN(NOD33LL)
w: 960 u w: 480 u 100%
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 114 114 0 0
Nets: 16802 16802 2 2
Instances: 1468 1468 0 0 MN(N12LL)
311 311 0 0 MN(NOD33LL)
2522 2522 1 0 MP(P12LL)
1 1 0 0 MP(P25LL)
206 206 0 0 MP(POD33LL)
2 2 0 0 Q(PNP25A25LL_SH)
0 0 0 2 C(CP)
4 4 0 0 rppo_ckt
127 127 0 0 rpposab_ckt
4 4 0 0 D(NDIO25LL)
8 8 0 0 D(PDIO25LL)
10849 10849 0 0 INV
1528 1528 0 0 NAND2
63 63 0 0 NAND3
29 29 0 0 NAND4
384 384 0 0 NOR2
59 59 0 0 NOR3
29 29 0 0 NOR4
91 91 0 0 AOI_2_1
80 80 0 0 AOI_2_1_1
136 136 0 0 AOI_2_2
5 5 0 0 AOI_2_2_1
19 19 0 0 AOI_2_2_2
14 14 0 0 AOI_3_1
10 10 0 0 AOI_3_2
155 155 0 0 OAI_2_1
76 76 0 0 OAI_2_1_1
79 79 0 0 OAI_2_2
15 15 0 0 OAI_2_2_1
2 2 0 0 OAI_2_2_2
14 14 0 0 OAI_3_1
12 12 0 0 OAI_3_2
4 4 0 0 OAI_3_3
1258 1258 0 0 SDW2
2002 2002 0 0 SDW3
3362 3362 0 0 SUP2
52 52 0 0 SUP3
74 74 0 0 SPDW_2_1
1 1 0 0 SPDW_2_2_2
35 35 0 0 SPUP_2_1
1 1 0 0 SPUP_2_2_2
62 62 0 0 SMN2
1 1 0 0 SMN3
4 4 0 0 SMP2
2 2 0 0 SMP3
33 33 0 0 SPMN((2+1)*1)
22 22 0 0 SPMP((2+1)*1)
------- ------- --------- ---------
Total Inst: 25215 25215 1 2
|
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2014-5-30 11:23:54