Cadence招聘Lead/Senior Verification/Design Engineer (数字前端验证和设计工程师）

kengteng

[url=]Cadence招聘Lead/Senior VerificationEngineer (数字前端验证)和Lead/Senior Design Engineer Location： SH/BJ更多职位信息敬请关注Cadence公众微信平台：Cadence中国招聘If you have interest, PLS send your updateCV to zhangyl@cadence.com   Position Description: Deliver/implement advancedverification solutions by utilizing Cadence’s Incisive Verification productportfolio. The engineer should be able to act as a strong team member andcontributor, leading team projects and initiatives. Exercise judgment within generallydefined practices and policies. Specific duties include: -- Deep understanding onASIC/SOC design flow-- Excellent knowledge ofadvanced verification methodology like eRM/OVM/UVM-- Familiar with Cadence’sIncisive Plan to Closure Methodology (IPCM)--Proficiency in SystemVerilog,  System C and/or e (Specman)-- Developing and usingVerification Components (eVC, OVC, UVC, VIP)-- Developing and usingassertion based verification and formal analysis methods--Skilled in scriptinglanguage, such as Perl, C shell, Makefile-- Assessing the projectverification requirements-- Operating in a lead roleregarding architecting and implementation of project        verification environment/solution.-- May coordinate/leadothers within the scope of a defined project Position Requirements: -- Must have BS degree with 6+ years of applicable experience, MS degreewith 4+ years of applicable experience in electrical engineering,microelectronics, comparable engineering science or solid state physics. -- Essential that theindividual demonstrates strong communication, verbal and written. Requires goodcommunication skills in English. Desirable Qualifications: -- A minimum of seven yearsrelevant experience in industry.-- Will have demonstratedhands-on experience and expertise with Cadence verification design tools orequivalent tools, flows and methodologies required to execute a verificationproject.-- Will have demonstratedsuccessful completion of 10+ verification projects as an individual contributor-Prefer to have DDR IPverification experience [/url]

Title: Lead/Senior Design Engineer (数字前端设计)

Job location: Shanghai/Beijing

更多职位信息敬请关注Cadence公众微信平台：Cadence中国招聘

Ifyou have interest, PLS send your update CV to zhangyl@cadence.com

Position Description:

Deliver/implementDDR IP. The engineer should be able to act as a strong team member andcontributor, leading team projects and initiatives. Exercise judgment withingenerally defined practices and policies.

Specific duties include:

- Beresponsible for building and leading a high-performance IC design team, owningthe IC micro-architecture, package and test platform development, refining theEDA design flow

-Proficiency in logic design, simulation, synthesis, STA and testing

-Proficiency in Verilog and its simulation environment

- Goodknowledge of IC design

* At leastfive years experience driving complex IC development projects, excellentcommunication skills and the uncanny ability to both lead and contribute in acooperative team environment.

  

Position Requirements:

1. EssentialQualifications: Must have BS degree with 6+ years of applicable experience, MSdegree with 4+ years of applicable experience in electrical engineering,microelectronics, comparable engineering science or solid state physics.

2. Essentialthat the individual demonstrates strong communication, verbal and written. 3. Requiresgood communication skills in English.

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