I guess "三个简并点" means the bandgap is lock at non-desire dc point.
If you have time, the following debug items will help to know the problem clearly:
1. use ideal resistor re-sim monte carlo analysis
==>it will help us to know the issue is res or not.
==>if the problem is res, force the res (may the width is too small)
2. check mos operation / current / node voltage when vref is not correct.
If hope these items will give some information.
mpig