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Although it's been four years since the publication of the first edition,
it's somewhat surprising to see that the basics of cache design have
remained largely intact. Although great strides have been made in the
number of transistors on the processor chip itself, with the bulk of these
going into the cache memory, we find that very small changes have
been made to the policies used by the processors' on-chip caches. With
the exception of some minor improvements in the complexity of the
handling of write cycles, the structures have remained relatively
straightforward. Nearly everything that is now being used was covered
by the first edition in detail.
So then, why do a second edition? No matter how timelessly they are
written, technology books constantly need to be revised, and this one is
no exception. Many of the example processors used in the original text
are now either obsolete, or promise to become obsolete in the very near
future. The first edition contained a complete chapter demonstrating
example cache designs which today's designers can implement more
elegantly with far fewer chips than they could have at the time of the
last publishing. In the introduction to the first edition I said that this
chapter "will become outdated much sooner than the others" (and I
was more correct than I expected). Furthermore, few of the processors
in these examples are used any longer with external cache chips, since
their higher speed successors are preferred now for use in high-
performance systems. I have, however, elected to retain a single one of
these caches, the oldest, incidentally, to illustrate in Chapter 1 that the
gate count for a true-to-life cache design is not all that high, and that
cache designs need not be shied away from.
I have also added a new Chapter 5 showing how others have
approached certain difficulties they have encountered. It is fun to see
how others have found their way around particularly thorny problems,
ones you might even encounter yourself. None of these solutions is
overly complex, but they show great amounts of ingenuity.
I have added words to the glossary and the text; however, the
discipline seems to be moving more and more toward uniformity,
probably owing to the greater amount of communications that now are
happening between cache designers. As fields become broader, and
communications between companies become more frequent and open,
company-specific buzzwords give way to more standard ones, and
people discover others' buzzwords before deciding that they need to
invent a new one of their own.
Finally, as opposed to the cacheless system I used to create the first
edition, the second edition is being crafted on a Windows 95 machine
using a 133 MHz Pentium with an 8KB primary cache and a 256KB
secondary cache. Surprisingly enough, the newer versions of the
software I am using to create the revised text and graphics slow things
down to the point that there is not all that much difference in speed at
the user interface between the new machine and the old.
Cache Memory Book, The, Second Edition - Jim Handy.pdf
(6.31 MB, 下载次数: 1754 )
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发表于 2014-3-24 08:37:26
