Power-Rail ESD Clamp (with Gate Leakage Consideration )

semico_ljj

Power-Rail ESD Clamp Circuits
with Gate Leakage Consideration in
Nanoscale CMOS Technology


Abstract   CMOS technology has been widely used to produce
many integrated circuits (ICs). However, the thinner gate oxide in
nanoscale CMOS technology seriously increases the difficulty of
electrostatic discharge (ESD) protection design. The power-rail
ESD  clamp  circuit  has  been  the  key  circuit  to  perform  the
whole-chip ESD protection scheme. Some ESD detection circuits
were developed to trigger on ESD devices across the power rails to
quickly discharge ESD current away from the internal circuits.
Therefore, on-chip ESD protection circuits must be designed with
the  consideration  of  standby  leakage  to  minimize  the  power
consumption and the possibility of malfunction to normal circuit
operation. The design of power-rail ESD clamp circuits with low
standby leakage current and high efficiency of layout area in
nanoscale  CMOS  technology  is  reviewed  in  this  paper.  The
comparisons among those power-rail ESD clamp circuits are also
discussed.

Index Terms Electrostatic discharge (ESD), gate leakage, layout
area, power-rail ESD clamp circuit.

Claire90

谢谢！

gubels

Reply 1 # semico_ljj


   howocharacterize

gubels

Reply 1 # semico_ljj


   Need cadence simulatiion setup...?

chenxiaoming

leel

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chuntian101

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核桃树

ths!!~~

efong

THANK YOU

favourate008

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