Cadence 招聘 Principal/Lead Design Engineer (数字前端)

kengteng

Title: Principal Design Engineer (数字前端设计)

Joblocation: Beijing/Shanghai

更多职位信息敬请关注Cadence公众微信平台：Cadence中国招聘

If you have interest, PLS send your update CV to zhangyl@cadence.com

PositionDescription:

Deliver/implement DDR IP. The engineer should beable to act as a strong team member and contributor, leading team projects andinitiatives. Exercise judgment within generally defined practices and policies.

Specificduties include:

- Be responsible for building and leading ahigh-performance IC design team, owning the IC micro-architecture, package andtest platform development, refining the EDA design flow

- Proficiency in logic design, simulation,synthesis, STA and testing

- Proficiency in Verilog and its simulationenvironment

- Good knowledge of IC design

* At least five years experience driving complexIC development projects, excellent communication skills and the uncanny abilityto both lead and contribute in a cooperative team environment.

  

PositionRequirements:

1. Essential Qualifications: Must have BS degreewith 10+ years of applicable experience, MS degree with 6+ years of applicableexperience in electrical engineering, microelectronics, comparable engineeringscience or solid state physics.

2. Essential that the individual demonstratesstrong communication, verbal and written. 3. Requires good communication skillsin English.