使用simvision察看ovm内的对象和信号

huanguestc002

使用的irun-input 中的tcl脚本如下

ovm_set "*" "recording_detail" OVM_FULL -config
ovm_phase -stop_at run
run
probe -create -shm worklib.ovm_pkg:vm_top_levels -depth all
run -clean
save  debug -overwrite
run
exit

仿真结束后使用 simvision -snapshot worklib.debug:sv 提示找不到snapshot file : worklib.debug:sv
snapshot file是生成了的 ，为什么找不到呢，实了多个路径执行simvision -snapshot worklib.debug:sv 都不行，
请问大家遇到过这样的问题没？

A1985

看一下log。。。

huanguestc002

回复 2# A1985
非常感激回复啊 。

ncsim> ovm_phase -stop_at run
Created stop 1
ncsim> run
OVM_INFO @ 0: reporter [RNTST] Running test imx_aclamp_auto_clamp_global_001...
*IRUN_INFO: LOCAL_FREQ SET 144.000000 Mhz
0 FS + 18 (stop 1: ovm_pkg:vm_phase_is_start = 1, ovm_pkg:vm_break_phase = run)
ncsim> probe -create -shm worklib.ovm_pkg:vm_top_levels -depth all
Created default SHM database ncsim.shm
Created probe 1
ncsim> run -clean
Ran until 0 FS + 19
ncsim>
ncsim> save  debug -overwrite
Message!     [SDI/Verilog]
    SDI/Verilog does not support save - no SDI information will be saved.
Current simulation time = 0
    "/tooltop/cadence/INCISIV/10.20.128/tools/ovm/ovm_lib/ovm_sv/sv/cdns_additions/cdns_recording.svh", 148: $sdi_create_fiber(name,t,scope);
Saved snapshot worklib.debug:sv
ncsim> run
......

上面是关键的log信息，红色部分是生成了snapshot file.

worklib所在路径：
INCA_libs  irun.lnx86.10.20.nc  irun.nc  worklib
xxxx-xxxx@login1-161% simvision -snapshot worklib.debug:sv
ippe: 10.20-s128: (c) Copyright 1995-2012 Cadence Design Systems, Inc.
ippe: *F,BADSNP: Unable to open the 'worklib.debug:sv' snapshot file..
报错打不开snapshot file.

A1985

回复 3# huanguestc002

ncsim worklib.test:sv -cdslib ../INCA_libs/irun.nc/cds.lib -hdlvar ../INCA_libs/irun.nc/hdl.var[size=11.666666030883789px]或
[size=11.666666030883789px]simviiosn -wave直接打开波形。。

naruto-edward

irun(64): 13.20-p002: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
TOOL:   irun(64)        13.20-p002: Started on Nov 22, 2016 at 10:50:40 CST
irun
        -c
        -timescale 1ns/10ps
        counter.v
        counter_tb.v
        -l comp.log
file: counter_tb.v
        module worklib.counter_tb:v
                errors: 0, warnings: 0
                Caching library 'worklib' ....... Done
        Elaborating the design hierarchy:
        Top level design units:
                counter_tb
        Building instance overlay tables: .................... Done
        Generating native compiled code:
                worklib.counter_tb:v <0x77011fcf>
                        streams:   1, words:   750
        Building instance specific data structures.
        Loading native compiled code:     .................... Done
        Design hierarchy summary:
                                  Instances  Unique
                Modules:                  2       2
                Registers:                4       4
                Scalar wires:             3       -
                Always blocks:            2       2
                Initial blocks:           2       2
                Simulation timescale:  10ps
        Writing initial simulation snapshot: worklib.counter_tb:v
TOOL:   irun(64)        13.20-p002: Exiting on Nov 22, 2016 at 10:50:40 CST  (total: 00:00:00)

借宝地问下，小白一个，这个irun就是跑不出来，log文件如上

naruto-edward

irun(64): 13.20-p002: (c) Copyright 1995-2014 Cadence Design Systems, Inc.
TOOL:   irun(64)        13.20-p002: Started on Nov 22, 2016 at 10:50:40 CST
irun
        -c
        -timescale 1ns/10ps
        counter.v
        counter_tb.v
        -l comp.log
file: counter_tb.v
        module worklib.counter_tb:v
                errors: 0, warnings: 0
                Caching library 'worklib' ....... Done
        Elaborating the design hierarchy:
        Top level design units:
                counter_tb
        Building instance overlay tables: .................... Done
        Generating native compiled code:
                worklib.counter_tb:v <0x77011fcf>
                        streams:   1, words:   750
        Building instance specific data structures.
        Loading native compiled code:     .................... Done
        Design hierarchy summary:
                                  Instances  Unique
                Modules:                  2       2
                Registers:                4       4
                Scalar wires:             3       -
                Always blocks:            2       2
                Initial blocks:           2       2
                Simulation timescale:  10ps
        Writing initial simulation snapshot: worklib.counter_tb:v
TOOL:   irun(64)        13.20-p002: Exiting on Nov 22, 2016 at 10:50:40 CST  (total: 00:00:00)

猪孩宝宝

请问楼主，问题解决了吗？我遇到了相同的问题。我感觉应该是出自UVM/OVM相关部分无法保存，但是我不确定，也不知道如何解决。请楼主指点