跪求 cadence615 verilog仿真问题

丝丁 · 发表于 2014-1-14 20:51:16

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cadence615 使用的是mmsim10 仿真器，但是进行不了verilog 仿真截图00.png

出现这样的报错

有没有人遇见过怎么解决？

Error found by spectre during AHDL read-in.
ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB/890_work61_PADCHLMC_DA12_veriloga_veriloga.va.d2a_ideal.ahdlcmi/Linux2.6.9-89.ELlargesmp+gcc/../ahdlcmi.out for details. If the compiler ran out of memory, use 'setenv CDS_CMI_COMPLEVEL 0', and try again. If the reason for the failure was a syntax error, contact your Cadence Customer Support representative with the netlist, log files, behavioral model files, and any other information that can help identify the problem.