开源软核学习笔记02（找到OC8051的帮助资料）——2014_1_8

oldbeginner

就在无法深入OC8051代码时，发现了自带的DOC文件"oc8051_design"，文件是在..\doc\src目录下，不注意会容易忽略。

浏览了一下文件，感觉这个文件会是理解OC8051的关键突破口。文件只有rev 0.2版的34页，主要内容分3个部分：

1、第一部分，介绍了8051的背景知识，比如输入输出接口；

2、第二部分，就是OC8051的模块设计，每一个模块的功能和相应接口的说明；

3、第三部分，简单介绍了验证文件testbench。

**********************************************************************************

第一部分，
接口输入输出名称：


name        direction        size        description
rst        input        1        reset
clk        input        1        clock

interrupt interface                  
int0        input        1        external interrupt 0
int1        input        1        external interrupt 1

timer/counter inputs        
t0        input        1        timer 0 input
t1        input        1        timer 0 input

serial interface                  
rxd        input        1        receive
txd        output        1        transmit

nterface to external program rom
ea        input        1        external access
rom_addr        output        16        rom address
op1        input        8        operation 1 input
op2        input        8        operation 2 input
op3        input        8        operation 3 input

nterface to external data ram
adr_o        output        16        address
stb_o        output        1        strobe
cyc_o        output        1        cyrcle
ack_I        input        1        acknowlege
dat_I        input        8        data input
dat_o        output        8        data output

port interface                  
p0_in        input        8        port 0 input
p1_in        input        8        port 1 input
p2_in        input        8        port 2 input
p3_in        input        8        port 3 input
p0_out        output        8        port 0 output
p1_out        output        8        port 1 output
p2_out        output        8        port 2 output
p3_out        output        8        port 3 output


********************************************
感觉图有些简陋。自己再找些。






*********************************************

除了接口，另外一个重点就是寻址方式：

-direct addressing (Data Memory and SFRs)

In direct addressing the operand isspecified by an 8-bit address field in the instruction. This address mode ispossible only for addressing internal Data RAM and SFRs.

- indirect addressing

In indirect addressing the instructionspecifies a register which contains the address of the operand. The addressregister for 8-bit addresses can be R0 or R1 of the selected register bank, orthe Stack Pointer. The address register for 16-bit addresses can only be the

16-bit “data pointer” register, DPTR.

Both internal and external RAM can beindirectly addressed.

- register instructionsSpecial instructions are used foraccessing four register banks (containing registers R0 to R7). Thisinstructions have a 3-bit register specification within the opcode of the instruction.
Register bank is selected by two bank selectbits in PSW.

- register- specific instructions/b]

Theseare instructions which are specific to a certain register and they don't needan address byte (they always operate with the same register). The most commonare those that use ACC register.

- immediate constants

In this address mode the value of a constant follows the opcode.

- indexed addressingIn this mode only Program Memory can be accessed. The address wanted issum of 16 bit base register (DPTR or PC) and accumulator (ACC).

oldbeginner

进入第二部分，首先是一个非常糟糕的结构图，字体小不说，重点也没有突出来，总之图画得很差。

然后，
First and maybe the mostimportant difference is pipeline with two stages. In first period instructionand its operands are fetched and decoded, second period is used for computingthe result and writing it to the memory.

oc8051采用两级流水线。第一级，取指令并译码；第二级计算结果并写入存储器。

We achieve this with additional set of registers which only task is to delay signals for one clockperiod. This is a must because the idea is that we set all control signals already in the first period and then delay the one that are not needed (forexample, address where the result will be saved) for one period.

利用使任务将信号延迟1个时钟周期的寄存器，就可以实现二级流水线。
所有的控制信号在第一阶段就已经准备好，然后延迟不需要的信号一个阶段。


One of important aspects is also bus control, which is handled by main module(oc8051_decoder). We achieve this with control signals which are connected tomultipleksers that are set at the beginning of each bus. With multipleksers we set who controls the bus at the moment.

利用主模块oc8051_decoder来控制总线。
http://baike.baidu.com/link?url= ... _CesxKz-BsuYK8CDeG_
控制信号连接多路复用器，通过多路复用器控制总线。

************************************************

然后进入各个模块介绍，

1、oc8051_top
Module oc8051_top is at the top of module hierarchy and represents interface with the environment. It does not contain any 'always' commands and is only used for interaction between modules and environment.

oc8051_top是最上层，不含有“always"指令，只用作接口。

2、oc8051_decoder
As it was already mentioned oc8051_decoder is main module. This module gets operation code from the Program Memory and then sets control signals.

oc8051_decoder是主要模块，它从程序存储器得到指令，然后设置控制信号。

There are two internal signals. First is two bit wide signal, state. This signal obviously holds information about the state, that is the state of the pipeline. Typical value for this signal is b00. This value is changed only when the execution of command in the pipeline is blocked(jumps …).

这里有两个内部信号。第一个是2 bit宽的信号，名称是state。这个信号控制流水线状态信息。该信号的典型值是 b00。当流水线中的指令被阻塞时（遇到jumps)，该信号的值发生改变。

Second internal signal is op,  this is registers in which we save operation code and is also needed only with instructions that take more then one clock period to complete (jumps again).

第二个内部信号是op，存在寄存器中的操作码，当指令执行需要多于一个时钟周期时，op才会被用到。

Module is composed from five 'always' commands:
-        first and longest contains 'case' sentence in which we get information in which state is   pipeline. With that information and with information about operation code we set control signals.
-        second 'always' is for remembering operation code
-        third is for setting signal state to desired value
-        forth 'always' takes care for output signal reti
-        and last 'always' command is for signal write_x

该模块由5个”always“组成：

1、利用case判断流水线状态，利用state和op来设置控制信号。

2、用来记住操作码。

3、将信号状态设置为期望值。

4、关注输出信号中断返回指令。http://baike.baidu.com/link?url= ... OPiQfNLZa9dKDgf2flK

5、信号write_x。

*********************************************
感觉学习方向正确了。

oldbeginner

3、oc8051_alu

Module oc8051_alu represents combinational logic for arithmetical and logical operations.
Module has three 8 bit input operands (third operand is needed only for computing the address for PC or DPTR) and three input signals. This three signals are carry, auxiliary carry and a signal which is used for bit addressable instructions. And there is also four bits wide input for operation code.

ALU算术逻辑单元。含有3个八位的输入操作数（第三个操作数只有在计算PC或DPTR地址时才会用到），和3个输入信号。
这三个输入信号分别是，进位；辅助进位；和用在位地址指令的信号。

还有四位宽的操作码输入。

Next operations are available:
•        OC8051_ALU_NOP – no operation
•        OC8051_ALU_ADD - adding
•        OC8051_ALU_SUB - substracting
•        OC8051_ALU_MUL - multiplying
•        OC8051_ALU_DIV - dividing
•        OC8051_ALU_DA – decimal adjust
•        OC8051_ALU_NOT – negation, bit negation
•        OC8051_ALU_AND – and, bit and
•        OC8051_ALU_XOR – exclusive or
•        OC8051_ALU_OR - or
•        OC8051_ALU_RL – rotacion left
•        OC8051_ALU_RLC – rotacion left with carry (operation swap nibbles)
•        OC8051_ALU_RR – rotacion right
•        OC8051_ALU_RRC – rotacion right with carry
•        OC8051_ALU_PCS – adding 16 bit unsigned number with 8 bit signed number (tows-complement)
•        OC8051_ALU_XCH – excange, first input is transfered to second output and vice versa. If carry is set only lowest halfs of bytes are changed

可以进行的运算如上。

Exact coding of operations is written in oc8051_defines.v file.

运算码在文件oc8051_defines.v中。

Output from module are two 8 bit results, carry, auxiliary carry and overflow.

输出是2个八位bit宽结果，还有进位，辅助进位和溢出。

For multiplying and dividing submodules oc8051_multiply and oc8051_divide are used. They both have 8 bit input bus and two 8 bit output buses for result and an output for carry.

乘法和除法子模块分别定义在oc8051_multiply 和 oc8051_divide 中。他俩都有八位宽的输入总线和2个八位宽输出总线，1个总线输出结果，另一个总线输出进位标志。

4、oc8051_pc

Module oc8051_pc is actually a program counter. It computes the value of address for next instruction.

oc8051_pc是程序计数器，http://baike.baidu.com/link?url=UR4Rd_kw9MMxtKeGf56MN_Kz-yGNe2DrdNQ0r87VdW-36hTvrGjJI0PbbdvHvOAO3mnESpskd7t_h-5N--B15q

Input in module is operation code with which we compute the value for address.

模块的输入是用来计算地址值的操作码。

There are also inputs that are used in case of jumps (op2 and op3 in case of absolute jumps, alu input for relative addressing),

还有用来万一jumps的输入（绝对跳转时，op2和op3，ALU输入作为相对地址）

there are also signals for choosing the source for new pc (pc_wr_sel) and a signal which is used if we input new address (wr).

还包括选择新程序计数器（pc_wr_sel）的信号，和输入新地址的信号。

The only output from module is 16 bit current value of program counter.

模块唯一的输出就是十六位宽的程序计数器中的数值。

jerrycao

Great.  I keep watching u .

oldbeginner

从论坛上下载的最新oc8051是不含oc8051_pc.v，原因暂时不明，第一版是有oc8051_pc.v的。

这些模块的具体内容放在后面分析，先按照帮助文件的组织方式把模块浏览一遍，对结构有个大概认识。

5、 oc8051_rom

Input in module is 16 bit address.

输入是十六位宽的地址。

Outputs are three 8 bit data buses and ea_int signal.

输出是八位宽的数据总线和ea_int 信号。

Input address is from first byte of data (data1), second and third byte (data2, data3) are on the following addresses.

输入地址来自数据data1的首字节，随后的地址是第二字节和第三字节（data2和data3）。//很奇怪，3x8=24不是很理解，先放着。

This is needed for uninterrupted functioning of pipeline.

以上对流水线非中断功能来说是必要的。

Ea_int signal is equal to external ea signal, it is activated if the used address is to big for internal Program Memory and we need to access external Program Memory.

ea_int等价于外部ea信号，当地址大于内部程序空间时，ea_int被激活，这样就可以访问外部程序空间。

******************************************************************

6、oc8051_comp

Function of module oc8051_comp is to compare two inputs and set output if the inputs are the same.

模块oc8051_comp的功能是比较两个输入，如果输入相等则设置输出。

Module is needed for computing conditions at conditional jumps.

计算条件跳转状态时，需要该模块。

There are different options for comparing the inputs:
-        ACC vs. zero
-        result of arithmetic operation vs. zero
-        carry
-        bit carry (from memory)

对比较输入，有不同的选项：
1、ACC 对 0
2、运算结果 对 0
3、进位
4、位进位（来自存储器）

These options are enough for all conditional jumps in 8051.

在8051中，这些选项应对条件跳转足够了。

Output is connected to oc8051_decoder input, where is transferred to pc_wr when needed.

输出连接oc8051_decoder的输入，当需要时输出转成pc_wr。

**********************************************************

7、oc8051_op_select

All data coming from Program Memory goes through this module.

所有来自程序空间的数据都要经过这个模块。

It has three assignments.

它有三项任务。

First assignment is to choose which memory will be used, internal or external.

第一个任务是选择访问内部空间还是外部空间。

In this assignment the module is functioning like a multiplekser: it has ea and ea_int signals for inputs (if anyone of this two signals is low there is a read cycle from external memory) and an output.

这项任务有点像多路复用器：对输入它有ea和 ea_int 信号 （当这两个信号任意一个低电位时，将是外部空间的读周期），还有一个输出。

Second assignment for this module is interrupt intake.

第二个任务是接收中断。

For this purpose this module, beside three 8 bit inputs, has also two input signals for receiving interrupts.

为了这个目的，除了3个八位bit的输入外，还有两个用来接收中断的输入信号。

These are signal int and 8 bit int_v.

这两个接收中断的信号是int 和 八位bit宽的 int_v。

We have an interrupt if int signal is set and on the 8 bit bus we receive address of interrupt program (upper 8 bits are zeros).

当int信号在八位bit宽总线上被置位时，产生一个中断，将会接收中断程序地址（头八位bit是0）。

At interrupt we check if the instruction currently executing is 'longer' then one clock cycle (input signal rd) and then LCALL operation code is sent to first output.

中断时，如果正在被执行的指令大于一个时钟周期（输入信号rd //不是很理解），然后LCALL操作码被送到第一个输出。

On other two outputs address of interrupt program is sent.

随后中断程序另两个输出的地址被发送。

Last assignment of this module is checking operation code and sending memory address, for writing the result, to the output.

最后一个任务是检查操作码和发送空间地址，这样可以把结果写到输出中。

This is used with instructions that need DPTR for computing results and with instructions that use B register.

需要DPTR计算结果的指令，和需要使用B寄存器的指令，和最后一个任务相关。

With this option for immediate addressing mode later on is achieved.

后面将会里利用这个选项作为直接地址寻址。

We have to be careful, because with this we have two different outputs for second operand, one for immediate operand in ALU and the other for direct addressing.

必须非常仔细，因为对第二个操作数可以有两个不同的输出，一个是ALU的立即操作数，另一个是直接地址。

*****************************************************************

8、oc8051_regX

Oc8051_regX modules represent X bit registers, which only function is to delay signal for one clock cycle.

这个模块表示 x位寄存器，只是用来让信号延迟一个时钟周期。

Besides input for clock and reset they also have data input and output.

除了时钟和复位输入外，同样有数据输入和输出。

****************************************************************

上面介绍了8个模块，下面的模块又分了两部分：

1、数据空间和特殊寄存器相关模块；

2、多路复用器相关模块。

oldbeginner

*******************************************
Data Memory and SFRs

这部分的模块都包含数据，这些模块共享同样的地址空间，因此他们有一些共同的输入信号：
这些信号有：

1、- clk        clock，时钟信号

2、- rst        reset. Reset values are written oc8051_defines.v file. 复位信号

3、- wr         writing 写操作信号

4、- wr_addr        address to where data is written 写地址信号

5、- data_in         input data 输入数据

6、- wr_bit        defines if the instruction is bit addressable 如果指令可操作位地址，则有该信号

7、- bit_in         bit input (for use only with bit addressable instructions and Data Memory) 位输入 （只用在位操作指令和位操作数据空间）

在下列情况下，特殊寄存器每时钟周期都要被检查：
1、如果有写周期（wr信号）；
2、如果位操作；
3、如果地址匹配要写入寄存器的数据。

地址可以不同，以便处理位操作指令或字节操作指令。物理地址定义在oc8051_defines.v文件中。

除了输入空间外，还有数据地址输入空间和数据输出空间。

特殊寄存器交互动画


内部数据存储器空间


内部地址空间


******************************************************

下面逐一介绍这些模块

1、oc8051_ram_top

This module contains Data Memory. It works like some sort of intermediate between ordinary memory and the kind of memory we need (capable of bit addressing).

这个模块包含数据空间。他工作起来有点像，介于普通空间和所需空间（能操作位地址）的某种空间。

In the bit addressing mode we have to use right bit from the address byte. When ther is a write cycle the whole byte has to be read, appropriate bit changed and all byte has to be written back to the memory.

在位地址模式中，我们必须从字节地址中得到正确的位数值。当写周期时，整个字节都要被读入；改变相应的位数值，整个字节再写回到空间。

Submodule of this module is oc8051_ram. This module depends on technology we use and it is an ordinary memory with 8 bit address. Simultaneus reading and writing is demanded because of the pipeline.

它的子模块是oc8051_ram。这个子模块取决与使用方法，是一个带八位bit宽地址的普通空间。
因为流水线缘故，要能同时读和写。

*****************************************************************

2、oc8051_acc

The most used SFR is Accumulator (ACC). Besides standard ports it also has 8 bit input for second ALU result (data2_in) and signal wad2 which activates writing of second result to register. There is another output for parity (p).

使用最多的特殊寄存器。
除了标准端口外，它还有八位宽的输入，这个输入用给第二个ALU结果（data2_in）；
还有一个wad2的信号，当把第二个结果写入寄存器时，该信号被激活。
还有另外一个输出，是为了奇偶校验。

*********************************************************************

3、oc8051_b_register

B register is simple bit addressable register without special features.

B寄存器是没有特殊功能的，简单的，位地址操作寄存器。

**********************************************************************

4、oc8051_psw

This module contains Program Status Word  (PSW) register . Beside standard inputs it also has input signal p (parity) from accumulator, auxiliary carry and overflow from ALU and signal set that defines what should be written to register.

这个模块包含程序状态字。
除了标准输入外，它还有来自ACC的信号p（奇偶）；
还有来自ALU的辅助进位和溢出信号；
并置位要写入寄存器的对应信号。

oldbeginner

5、oc8051_dptr

This module contains 16 bit Data Pointer. It has two 8 bit outputs (data_hi and data_lo) and 8 bit input bus for second ALU result and 2 bit signal that is used when we use instructions that treat DPTR as 16 bit register.
This register is not bit addressable.

这个模块含有十六位bit宽的数据指针。
它有两个八位bit宽的输出（data_hi 和 data_lo）。
给第二个ALU结果用的八位bit宽的输入总线。
两位bit宽的信号，当指令需要使用DPTR作为十六位bit宽寄存器时，该信号被激活。
该寄存器不能进行位地址操作。

*************************************************************

6、oc8051_sp

This module represents Stack Pointer. Besides stndard inputs it also has two input signals connected to oc8051_decoder. This two signals define from where read or write address will be taken.

该模块表示堆栈指针。
除了标准输入外，他还有两个输入信号，连接到oc8051_decoder。
这两个输入信号定义了读或者写的地址。



***************************************************************

7、oc8051_ports

This module takes care of input-output ports. It has four 8 bit input buses and four 8 bit output buses. This signals are used for communicating with environment. Input to module is also 8 bit current address. This module also has rmw signal, which tells us if the instruction is so called read-modify-write instruction. With these instructions we don't read input pins of module but registers of output ports.

这个模块关注输入——输出端口。
它有八位宽的输入总线和4条八位宽的输出总线。
当和外界交流时，就使用这里的信号。
模块的输入是八位宽的目前地址。
该模块有个rmw信号，用来表示指令是否是——读—更改—写——指令。

如果有下面列出的指令，则不读模块的输入端口，而是读输出端口的寄存器。
These instructions are:
-        ANL
-        ORL
-        XRL
-        JBC
-        CPL
-        INC
-        DEC
-        DJNZ
-        MOV PX.Y, C
-        CLR PX.Y
-        SETB PX.Y

***********************************************************************

8、oc8051_tc


This module contains the description of oc8051 timers. There are two timers: Timer/Counter 0 (T/C 0) and Timer/Counter 1 (T/C 1). Both timers are 16 bit long and are represented by two 8 bit registers each (TL0 and TH0 for T/C 0, TL1 and TH1 for T/C 1). This module also contains SFR TMOD, which defines timer modes.



Four input signals ie0, ie1, tr0, tr1 represent conditions that activate timers. There are also two output signals tf0 and tf1, those signals set overflow flags in TCON register and 8 bit output bus (data_out) from which we can read current value of the chosen register (TMOD, TL0, TH0, TL1, TH1).
Timers can operate in four different modes:
mode 0: both timers are 8-bit counters with divide-by-32 prescaler, that gives us a 13-bit counter. Only lower five bits of TLx register are used.
mode 1: both registers are 16-bit counters
mode 2: THx represents 8-bit counter which is filled with TLx content at overflow
mode 3: in this mode t/c1 just holds constant value. While t/c0 is used as two separate 8-bit counters. TH0 uses control signals from timer0 (TR0 in TF0), while TL0 is using control signals from timer1 (TR1 in TF1).  

四个输入信号是ie0，ie1，tr0，tr1，表示激活定时器的状态。
另外还有两个输出信号tf0和tf1，这两个信号用来设置TCON寄存器和八位输出总线的溢出标志。
定时器有四种工作模式（因为用过51的c编程，这部分就熟悉了，51相关的资料真得很多，51软核除外）

oldbeginner

9、oc8051_int

This is interrupt module. It accepts interrupt requests and under defined conditions dispatches these requests to the processor. In oc8051 core we have five different interupt sources and each has special address for its service rutine.

中断模块。该模块接收中断请求，然后根据已定义的状态，调度请求到处理器中。
这里定义了五种不同中断源，每一种的中断函数都有自己的独一的地址。

These addresses are:
-        external interrupt 0 (0003H)
-        timer 0 overflow (000BH)
-        external interrupt 1 (0013H)
-        timer 1 overflow (001BH)
-        serial port interrupt (0023H)



该模块包含三个特殊功能寄存器：
-        timer control register (TCON), contains interrupt flags



-        interrupt enable (IE), enables or disables



-        interrupt priority (IP), in this register priority of specific interrupts is set. oc8051 uses two priority levels. When appropriate bit is set the priority of its interrupt source is increased.



Module has five interrupt inputs, each for every interrupt source. There are two more input signals, signal reti which is set when interrupt ends and signal ack which is set high when processor vectors to interrupt rutine. Module also has 8 bit bus that is used for fetching interrupt vector address.

模块有五个输入中断，每一个对应一个中断源。
还有另外两个输入信号，当中断结束时，信号reti置位；当处理器向量打断任务时，信号ack置位。
模块还有八位总线用来读取中断向量地址。



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10、oc8051_uart

This module contains oc8051 serial interface (uart). Besides standard inputs it also has an input for receive signal (rxd) and an input for transmit signal (txd). These two signals are also outputs from the processor. There is also a  timer1 overflow input and an output for interrupts.

该模块包含8051串口接口。
除了标准输入外，还有表示接收的输入信号（rxd）和表示发送的输入信号（txd）。
这两个信号是处理器的输出。
另外还有定时器1的溢出输入和表示中断的输出。

Modul contains three SFRs: serial control (scon), serial data buffer (sbuf) and power control (pcon).







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11、oc8051_indi_addr

This module does not contain any SFR but it still contains a part of Data Memory. It contains data from R0 and R1 registers from all register banks. This registers are used for indirect addressing. Input in module are two bits with which we choose a specific register bank and last part of operation code for choosing between registers R0 or R1. This is needed so the address of operand at indirect addressing is already available in first clock cycle and there is no need to stop the pipeline.

该模块不包含任何特殊功能寄存器，但是仍旧包含一部分数据空间。
来自R0和R1寄存器的数据，来自寄存器缓冲区的数据都包含在这个模块内。
这个模块用于间接寻址。
输入在特定的寄存器缓冲区占据两位bit，操作码的最后一部分用来选择寄存器R0或R1。
因此在直接寻址中，在第一时钟阶段，操作数已经就位，没有必要停止流水线。

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12、oc8051_ram_sel

This module represents a multiplekser which on the base of a read address sends correct data to the data bus. We can choose between data from the memory or from any of the specail registers. This ensures that we get right data even when addressing SFRs (direct or indirect addressing).

该模块代表多路复用器，基于该复用器，读入的指针能够将正确的数据传给数据总线。这样就可以选择空间中的数据或者特殊寄存器中的数据。

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数据空间和特殊功能寄存器模块就理解完了，一共有十二个模块。
下一部分是Multipleksers相关模块。

coding_ali

嗯，找的比较详细哈，但是感觉这份文档（包括程序的帮助文档很少）比较简略，没找到如何取指的。。。。晕。

oldbeginner

浏览了文档，该文档只是将各个模块串了起来，这样就有一个整体认识。对接下来的分块学习很重要。

怎样取指令还要看模块内部代码或者其它资料。