招3～5年的验证工程师[上海]

zzly_c

Duties will include functional verification of mixed-signal IP. Candidate will be expected to contribute to design and development of System Verilog based verification environment and will be responsible for verification closure of block/chip/system level functions for mixed signal based IP. Experience with System Verilog and functional coverage methodologies is required. Must be willing to follow a disciplined verification methodology and to work closely with a multi-location, international design team. Excellent teamwork and communication skills are required.

Requirements/Qualifications (Education)
- BSEE with 3-5+ years of design and/or verification experience required, MSEE preferred.
- Required knowledge and skills:
- Expertise in System Verilog required
- Good understanding of Digital Signal Processing
- Good understanding of Analog and Digital Circuits
- Very good analytical/debugging skill
- Good verbal and written communication skills

上海外企3～5年的验证工程师，帮内部推荐。
有需求的可以私聊： 173745573@qq.com