Cadence BJ 招聘资深数字前端验证工程师

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Cadence BJ 招聘资深数字前端验证工程师

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If you haveinterest, PLS send your update CV to zhangyl@cadence.com

Title: Principal/Lead Verification Engineer

Position Description:

Deliver/implement IP design. The engineershould be able to act as a strong team member and contributor.

Specific duties include:

- Proficiency in logic design, simulation,synthesis, STA and testing

- Proficiency in Verilog and its simulationenvironment

At least five years experience driving complexIC development projects, excellent communication skills and the uncanny abilityto both lead and contribute in a cooperative team environment is required.

PositionRequirements:         

BSdegree with 6~10+ years of applicable experience, MS degree with 4~7+ years ofapplicable experience in electrical engineering, microelectronics, comparableengineering science or solid state physics. Essential that the individualdemonstrates strong communication, verbal and written. Requires goodcommunication skills in English.