Location: Chengdu
Job Description:
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ASIC physical implementation including DFT flow, synthesis, timing closure, low power design and ECO.
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Responsible for implementation of tool flow, CAD methodologies development, script/flow generation, etc.
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Tool evaluation for developing new tool flow, work on related day to day timing backend and closure
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Scripting, UNIX shell, TCL
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Timing closure at functional reg to reg and IO timing, static timing & crosstalk analysis, etc.
Qualifications:
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BSEE/MSEE + 3-5 years hands on Physical Implementation or Physical Design Experience
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Good skill of English for reading, writing and speaking.
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RTL & gate synthesis with Cadence RC (RTL Compiler).
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Experience of supporting DFT and Low Power design with Cadence EDI Platform
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Static timing, timing closure, noise analysis, etc.
- Experience of Cadence low power design, multi-power domain design is a plus.
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