猎头热招上海职位——IC Design Leader/Manager/Engineer

bestgrace

IC Design Leader/Manager：
Responsibilities:
1.Lead other Design Engineers in a team to meet the company's objectives；
2. Design and implement digital communication system blocks and whole chip including specification trade-offs and optimization, micro-architecture, RTL coding, Synthesis, STA and simulation, chip testing and characterization.
3.This is a full-time position with solid equity opportunity.
Requirements:
1.5+ years of experience in Verilog/Synthesis-based ASIC Design for mass production IC chipsExperience with project and team management
2.Experience from front-end to back-end (RTL, synthesis, verification, and test support) with data networking ASIC(Ethernet, TCP/IP)
3.Verilog language and simulation verification experience
4.Logic Synthesis and Static Timing Analysis
5.Interface with Place and Route and back-annotated simulation verification
6.Team-work spirit, and with a strong drive to excel



IC Design Engineer：
Responsibilities:
1.Work with other Design Engineers to meet the company's objectives；
2.Design and implement digital communication system blocks and whole chip including specification trade-offs and optimization, micro-architecture, RTL coding, Synthesis, simulation and verification, chip testing and characterization.
3.This is a full-time position with solid equity opportunity.
Requirements:
1.3+ years of experience in Verilog/Synthesis-based ASIC Design
2.Experience with front to back (RTL, synthesis, verification, and test support) with data networking ASIC(Ethernet, TCP/IP)
3.Verilog language and simulation verification experience
4.Logic Synthesis and Static Timing Analysis
5.Interface with Place and Route and back-annotated simulation verification
6.Team-work spirit, and with a strong drive to excel

E-Mail: bestgrace@qq.com

QQ: 2043753191

新浪blog: http://blog.sina.com.cn/u/1767088102