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AMD Beijing DFx team 招聘!!!
简历发至:Neil.Hao@amd.com
代友发文,勿站内
Position: MTS/Sr Design Engineer - DFT
Job Description:
Qualified candidate will perform some or all functions below:
1. Participate in SOC full Chip DFT feature and architecture definition
2. Responsible for DFT specification generation and review
3. Implement SOC DFT function including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
4. Perform verification on all DFT structures
5. Generate DFT related timing constraints and work with PD team for timing closure
6. Generate and verify DFT structural patterns and functional patterns
7. Participate in ATE bring-up and debug the DFT patterns on ATE
8. Design and implement other DFX (debug, characterization, yield etc) logics
Requirements/Qualifications:
- BS in EE & CS. MS preferred, with 3+ years experience.
- Hands on working experience on ASIC DFT design and verification
- Familiar with entire ASIC design flow
- Experience with micro processor design a big plus
- Should have strong problem solving skills
- Good English hearing, speaking, reading and writing capabilities
- Good communication skills |
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