AMD （Beijing） DFX team 招聘Sr/MTS verification engineer

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联系：xin1.zhang@amd.com
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Job Title:     Senior/MTS Design Verification Engineer for DFX team
City/Town:     Beijing
Country:     China


Job Description:     Responsibility:
We are currently looking for  Sr/Staff  Engineers who will be responsible for all aspects of verification on next generation integrated processors (CPU + GPU + Multi Media), including developing testbenches, modeling, assertions/checkers/monitors, test plan & test development, regressions, and infrastructure development. Responsibility includes participating in the pre-silicon blocks, chip, multi-chip and system level verification strategy:
-        Verification of SoC level design using random methodologies – Test Planning, Implementation and Execution.
-        Develop System Verilog (OVM) random sequences and methods.
-        Maintain and Interface with existing random generators, models and APIs
-        Integration of random modules to various testbenches.
-        Executing verification through directed and random tests for its functionality and interface protocols and tracking bug reports. Creation of the needed test libraries, test API, simulation models. Debugging regression failures and identify the cause.
-        Strong documentation and communication skills.
-        Ability to work well in a dynamic, fast-paced, pressure filled, across multiple sites North America and Asia
-        Flexible in terms of responsibilities and hours.


Requirement:
-        3+ years experience with Master degree or 5+ years experience with Bachelor degree.
-        Complex ASIC/SOC Design Verification, direct experience in SOC or Processor (GPU or CPU) or Industry bus standard (PCI-e, MC, HT) or multimedia/video is preferred.
  -        Good knowledge of SystemVerilog and OVM is a plus.
  -        Good knowledge of DFT is a big plus.
-        Good knowledge of  Verilog/C/C++/System C/SystemVerilog.
-        Verification insights into random techniques.
-        Verification of large scale ASICs.
-        Experience in power verification is an asset.
-        Verification of Virtualization Components is an asset.
-        C and C++ software development and scripting languages (Perl, C Shell, Makefile, …) experience.
-        Background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA).